AD4082
推荐用于新设计20-Bit, 10 MSPS, Low Noise, Low Power SAR ADC
Low Noise, Low Power, Fast Precision SAR ADC
- 产品模型
- 3
概述
- 20-bit resolution, no missing codes
- Throughput: 10MSPS, 135ns conversion latency
- Noise spectral density: 17.56nV/√Hz,−161.6dBFS/Hz
- Low 1/f, low frequency noise (0.1Hz to 10Hz): 174nV rms
- Low power: 58.6mW typical at 10MSPS
- INL: ±3ppm (typ), ±6ppm (max)
- Dynamic range: 94.7dBFS
- SNR/THD
- 94.4dB (typ)/−114.5dB (typ) at fIN = 1kHz
- 93.8dB (typ)/−103dB (typ) at fIN = 1MHz
- Easy Drive
- 6V p-p differential input range
- Continuous signal acquisition
- Linearized, 5μA/MSPS input current
- Integrated, low-drift reference buffer and decoupling
- Integrated VCM generation
- Digital features and data interface
- Conversion result FIFO, 16K sample depth
- Digital averaging filter with up to 210 decimation
- SPI configuration
- Configurable data interface
- Single lane, DDR, serial LVDS, 200Mbps per lane
- Dual lane, DDR, serial LVDS, 100Mbps per lane
- Single/quad lane SPI data interface
- Package
- 49-ball, 5mm × 5mm CSP_BGA, 0.65mm pitch
- Integrated supply decoupling capacitors
- Operating temperature range: −40°C to +85°C
The AD4082 is a high speed, low noise, low distortion, 20-bit, Easy Drive, successive approximation register (SAR) analog-to-digital converter (ADC). Maintaining high performance (signal-to-noise and distortion (SINAD) ratio > 92dBFS) at signal frequencies in excess of 1MHz enables the AD4082 to service a wide variety of precision, wide bandwidth data acquisition applications. Simplification of the input anti-alias filter design can be accomplished by applying oversampling along with the integrated digital filtering and decimation to reduce noise and lower the output data rate for applications that do not require the lowest latency of the AD4082.
The AD4082 Easy Drive features reduce both signal chain complexity and power consumption while enabling greater channel density and flexibility in companion component selection. The product input structure was designed to minimize any input dependent signal currents, therefore reducing any converter induced settling artifacts. The continuous acquisition architecture allows settling across the entire conversion cycle, easing ADC driver settling and bandwidth requirements as compared to other high-speed data converters.
The AD4082 includes several elements that simplify data converter integration: a low drift reference buffer, low dropout (LDO) regulators to generate ADC core and digital interface supply rails, and a 16K result data first-in first out (FIFO) that can greatly reduce the load on the digital host. Additionally, critical supply and reference decoupling capacitors are integrated in the package to ensure optimum performance, simplify printed circuit board (PCB) layout, and reduce the overall solution footprint.
APPLICATIONS
- Digital imaging
- Cell analysis
- Spectroscopy
- Automated test equipment
- High speed data acquisition
- Digital control loops, hardware in the loop
- Power quality analysis
- Source measurement units
- Electron and X-ray microscopy
- Radar level measurement
- Nondestructive test
参考资料
视频 1
器件驱动器 1
在线研讨会 2
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| 产品型号 | 引脚/封装图-中文版 | 文档 | CAD 符号,脚注和 3D模型 |
|---|---|---|---|
| AD4082BBCZ | 49-ball CSP_BGA (5 mm x 5 mm x 1.33 mm) | ||
| AD4082BBCZ-RL | 49-ball CSP_BGA (5 mm x 5 mm x 1.33 mm) | ||
| AD4082BBCZ-RL7 | 49-ball CSP_BGA (5 mm x 5 mm x 1.33 mm) |
软件资源
Evaluation Software 1
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硬件生态系统
| 部分模型 | 产品周期 | 描述 |
|---|---|---|
| 差分放大器 2 | ||
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| 电源系统管理(PSM)和时序控制器 1 | ||
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| 基准电压源 2 | ||
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| 监控电路和复位器IC 1 | ||
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| 开关稳压器和控制器 3 | ||
|
LT8604/ LT8604C |
高效42V/120mA同步降压 | |
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| 扇出缓冲器和分路器 1 | ||
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| 锁相环(PLL)频率合成器 1 | ||
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| 线性稳压器 6 | ||
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| LT3045 | 推荐用于新设计 | 20V、500mA、超低噪声、超高 PSRR 线性稳压器 |
| ADP150 | 量产 | 超低噪声、150 mA CMOS线性调节器 |
| MAX38912 | 推荐用于新设计 | 具有低功耗模式的11µVRMS低噪声、500mA LDO线性稳压器 |
| 运算放大器 1 | ||
| ADA4899-1 | 量产 | 单位增益稳定、超低失真、1 nV/√Hz电压噪声、高速运算放大器 |
工具及仿真模型
IBIS 模型 1
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