AD9253
Info : RECOMMENDED FOR NEW DESIGNS
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AD9253

Quad, 14-Bit, 80 MSPS/105 MSPS/125 MSPS Serial LVDS 1.8 V Analog-to-Digital Converter

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Info : RECOMMENDED FOR NEW DESIGNS tooltip
Info : RECOMMENDED FOR NEW DESIGNS tooltip
Part Details
Part Models 8
1ku List Price Starting From $80.76
Features
  • 1.8 V supply operation
  • Low power: 110 mW per channel at 125 MSPS with scalable power options
  • SNR = 74 dB (to Nyquist); SFDR = 90 dBc (to Nyquist)
  • DNL = ±0.75 LSB (typical); INL = ±2.0 LSB (typical)
  • Serial LVDS (ANSI-644, default) and low power, reduced signal option (similar to IEEE 1596.3)
  • 650 MHz full power analog bandwidth
  • 2 V p-p input voltage range
  • Serial port control
    • Full chip and individual channel power-down modes
    • Flexible bit orientation
    • Built-in and custom digital test pattern generation
    • Multichip sync and clock divider
    • Programmable output clock and data alignment
    • Programmable output resolution
    • Standby mode
Additional Details
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The AD9253 is a quad, 14-bit, 80 MSPS/105 MSPS/125 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 125 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.

The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.

The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individual-channel power-down is supported and typically consumes less than 2 mW when all channels are disabled. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable output clock and data alignment and digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).

The AD9253 is available in a RoHS-compliant, 48-lead LFCSP. It is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent.

PRODUCT HIGHLIGHTS

  1. Small Footprint. Four ADCs are contained in a small, spacesaving package.
  2. Low power of 110 mW/channel at 125 MSPS with scalable power options.
  3. Pin compatible to the AD9633 12-bit quad ADC.
  4. Ease of Use. A data clock output (DCO) operates at frequencies of up to 500 MHz and supports double data rate (DDR) operation.
  5. User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirements

APPLICATIONS

  • Medical ultrasound
  • High speed imaging
  • Quadrature and diversity radio receivers
  • Test equipment
Part Models 8
1ku List Price Starting From $80.76

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Documentation

Documentation

Part Model Pin/Package Drawing Documentation CAD Symbols, Footprints, and 3D Models
AD9253BCPZ-105
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AD9253BCPZ-125
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AD9253BCPZ-80
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AD9253BCPZRL7-105
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AD9253BCPZRL7-125
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AD9253BCPZRL7-80
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AD9253TCPZ-125EP
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AD9253TCPZR7-125EP
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Product Lifecycle

PCN

Feb 1, 2024

- 24_0009

Qualification of alternative Wafer Fab for TSMC 0.18um Mixed Signal CMOS Process

AD9253BCPZ-105

PRODUCTION

AD9253BCPZ-125

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AD9253BCPZ-80

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AD9253BCPZRL7-105

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AD9253BCPZRL7-125

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AD9253BCPZRL7-80

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Filter by Model

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Part Models

Product Lifecycle

PCN

Feb 1, 2024

- 24_0009

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Qualification of alternative Wafer Fab for TSMC 0.18um Mixed Signal CMOS Process

AD9253BCPZ-105

PRODUCTION

AD9253BCPZ-125

PRODUCTION

AD9253BCPZ-80

PRODUCTION

AD9253BCPZRL7-105

PRODUCTION

AD9253BCPZRL7-125

PRODUCTION

AD9253BCPZRL7-80

PRODUCTION

Software & Part Ecosystem

Software & Part Ecosystem

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Evaluation Kit

Evaluation Kits 2

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HSC-ADC-EVALCZ

FPGA-Based Data Capture Kit

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HSC-ADC-EVALCZ

FPGA-Based Data Capture Kit

FPGA-Based Data Capture Kit

Features and Benefits

  • 64kB FIFO Depth
  • Works with single and multi-channel ADCs
  • Use with VisualAnalog® software
  • Based on Virtex-4 FPGA
  • May require adaptor to interface with some ADC eval boards
  • Allows programming of SPI control Up to 644 MSPS SDR / 800MSPS DDR Encode Rates on each channel
  • DDR Encode Rates on each channel

Product Detail

The HSC-ADC-EVALCZ high speed converter evaluation platform uses an FPGA based buffer memory board to capture blocks of digital data from the Analog Devices high speed analog-to-digital converter (ADC) evaluation boards. The board is connected to the PC through a USB port and is used with VisualAnalog® to quickly evaluate the performance of high speed ADCs. The evaluation kit is easy to set up. Additional equipment needed includes an Analog Devices high speed ADC evaluation board, a signal source, and a clock source. Once the kit is connected and powered, the evaluation is enabled instantly on the PC.
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EVAL-AD9253

AD9253 Evaluation Board

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EVAL-AD9253

AD9253 Evaluation Board

AD9253 Evaluation Board

Product Detail

The AD9253CE01A is an evaluation board for the AD9253-125 and the AD9633-125, quad 14 and 12-bit ADCs. This reference design provides all of the support circuitry required to operate the devices in their various modes and configurations. It is designed to interface directly with the HSC-ADC-EVALC data capture card, allowing users to download captured data for analysis. The Visual Analog software package, which is used to interface with the device's hardware, allows users to download captured data for analysis with a user-friendly graphical interface. The SPI Controller software package is also compatible with this hardware, and allows the user to access the SPI programmable features of the AD9253 and AD9633. User guide UG-328 provides documentation and instructions to configure the device for performance evaluation in the lab. (WIKI Site)


The AD9253 and AD9633 data sheets provide additional information related to device configuration and performance, and should be consulted when using these tools. All documents and Visual Analog and SPI Controller are available at the High Speed ADC Evaluation Boards page. For additional information or questions, please email highspeed.converters@analog.com.
Tools & Simulations

Tools & Simulations 4

Reference Designs

Reference Designs 1

Basic Block Diagram of Summing Four ADC in Parallel

14-Bit, 125 MSPS Quad ADC with SNR Enhanced by Post Digital Summation

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