Instrumenting 5G

The AD9164¹ is a high performance, 16-bit digital-to-analog converter (DAC) and direct digital synthesizer (DDS) that supports update rates to 6 GSPS. The DAC core is based on a quad-switch architecture coupled with a 2× interpolator filter that enables an effective DAC update rate of up to 12 GSPS in some modes. The high dynamic range and bandwidth makes these DACs ideally suited for the most demanding high speed radio frequency (RF) DAC applications.

The DDS consists of a bank of 32, 32-bit numerically controlled oscillators (NCOs), each with its own phase accumulator.

When combined with a 100 MHz serial peripheral interface (SPI) and fast hop modes, phase coherent fast frequency hopping (FFH) is enabled, with several modes to support multiple applications.

In baseband mode, wide analog bandwidth capability combines with high dynamic range to support DOCSIS 3.1 cable infrastructure compliance from the minimum of one carrier up to the full maximum spectrum of 1.791 GHz of signal bandwidth. A 2× interpolator filter (FIR85) enables the AD9164 to be configured for lower data rates and converter clocking to reduce the overall system power and ease the filtering requirements. In Mix-Mode^™ operation, the AD9164 can reconstruct RF carriers in the second and third Nyquist zones up to 7.5 GHz while still maintaining exceptional dynamic range. The output current can be programmed from 8 mA to 38.76 mA. The AD9164 data interface consists of up to eight JESD204B serializer/deserializer (SERDES) lanes that are programmable in terms of lane speed and number of lanes to enable application flexibility.

An SPI interface configures the AD9164 and monitors the status of all registers. The AD9164 is offered in a 165-ball, 8 mm × 8 mm, 0.5 mm pitch CSP_BGA package, and a 169-ball, 11 mm × 11 mm, 0.8 mm pitch, CSP_BGA package, including a leaded ball option.

Product Highlights

1. High dynamic range and signal reconstruction bandwidth supports RF signal synthesis of up to 7.5 GHz.
2. Up to eight lanes JESD204B SERDES interface flexible in terms of number of lanes and lane speed.
3. Bandwidth and dynamic range to meet DOCSIS 3.1 compliance and multiband wireless communications standards with margin. 

Applications

• Broadband communications systems
  
  • DOCSIS 3.1 CMTS/ video on demand (VOD)/edge quadrature amplitude modulation (EQAM)
• Wireless communications infrastructure
  
  • W-CDMA, LTE, LTE-A, point to point

The AD9213 is a single, 12-bit, 6 GSPS/10.25 GSPS, radio frequency (RF) analog-to-digital converter (ADC) with a 6.5 GHz input bandwidth. The AD9213 supports high dynamic range frequency and time domain applications requiring wide instantaneous bandwidth and low conversion error rates (CER). The AD9213 features a 16-lane JESD204B interface to support maximum bandwidth capability.

The AD9213 achieves dynamic range and linearity performance while consuming <4.6 W typical. The device is based on an interleaved pipeline architecture and features a proprietary calibration and randomization technique that suppresses interleaving spurious artifacts into its noise floor. The linearity performance of the AD9213 is preserved by a combination of on-chip dithering and calibration, which results in excellent spurious-free performance over a wide range of input signal conditions. 

Applications that require less instantaneous bandwidth can benefit from the on-chip, digital signal processing (DSP) capability of the AD9213 that reduces the output data rate along with the number of JESD204B lanes required to support the device. The DSP path includes a digital downconverter (DDC) with a 48-bit, numerically controlled oscillator (NCO), followed by an I/Q digital decimator stage that allows selectable decimation rates that are factors of two or three. For fast frequency hopping applications, the AD9213 NCO supports up to 16 profile settings with a separate trigger input, allowing wide surveillance frequency coverage at a reduced JESD204B lane count.

The AD9213 supports sample accurate multichip synchronization that includes synchronization of the NCOs. The AD9213 is offered in a 192-ball ball grid array (BGA) package and is specified over a junction temperature range of −20°C to +115°C.

The AD9172 is a high performance, dual, 16-bit digital-to-analog converter (DAC) that supports DAC sample rates to 12.6 GSPS. The device features an 8-lane, 15 Gbps JESD204B data input port, a high performance, on-chip DAC clock multiplier, and digital signal processing capabilities targeted at single-band and multiband direct to radio frequency (RF) wireless applications.

The AD9172 features three complex data input channels per RF DAC that are bypassable. Each data input channel includes a configurable gain stage, an interpolation filter, and a channel numerically controlled oscillator (NCO) for flexible, multiband frequency planning. The device supports up to a 1.5 GSPS complex data rate per input channel and is capable of aggregating multiple complex input data streams up to a maximum complex data rate of 1.5 GSPS. Additionally, the AD9172 supports ultrawide bandwidth modes bypassing the channelizers to provide maximum data rates of up to 3.08 GSPS (with 16-bit resolution) and 4.1 GSPS (with 12-bit resolution).

The AD9172 is available in a 144-ball BGA_ED package.

Product Highlights

1. Supports single-band and multiband wireless applications with three bypassable complex data input channels per RF DAC at a maximum complex input data rate of 1.5 GSPS. One independent NCO per input channel.
2. Ultrawide bandwidth channel bypass modes supporting up to 3 GSPS data rates with 16-bit resolution and 4 GSPS with 12-bit resolution.
3. Low power dual converter decreases the amount of power consumption needed in high bandwidth and multichannel applications.

Applications

• Wireless communications infrastructure
  • Multiband base station radios
  • Microwave/E-band backhaul systems
• Instrumentation, automatic test equipment (ATE)
• Radars and jammers

The AD9208 is a dual, 14-bit, 3 GSPS analog-to-digital converter (ADC). The device has an on-chip buffer and a sample-and- hold circuit designed for low power, small size, and ease of use. This product is designed to support communications applications capable of direct sampling wide bandwidth analog signals of up to 5 GHz. The −3 dB bandwidth of the ADC input is 9 GHz. The AD9208 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.

The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. The analog input and clock signals are differential inputs. The ADC data outputs are internally connected to four digital downconverters (DDCs) through a crossbar mux. Each DDC consists of up to five cascaded signal processing stages: a 48-bit frequency translator (numerically controlled oscillator (NCO)), and up to four half-band decimation filters. The NCO has the option to select preset bands over the general-purpose input/output (GPIO) pins, which enables the selection of up to three bands. Operation of the AD9208 between the DDC modes is selectable via SPI-programmable profiles.

In addition to the DDC blocks, the AD9208 has several functions that simplify the automatic gain control (AGC) function in a communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect control bits in Register 0x0245 of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input. In addition to the fast detect outputs, the AD9208 also offers signal monitoring capability. The signal monitoring block provides additional information about the signal being digitized by the ADC.

The user can configure the Subclasss 1 JESD204B-based high speed serialized output in a variety of one-lane, two-lane, four- lane, and eight-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multidevice synchronization is supported through the SYSREF± and SYNCINB± input pins.

The AD9208 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 3-wire serial port interface (SPI).

The AD9208 is available in a Pb-free, 196-ball BGA, specified over the −40°C to +85°C ambient temperature range. This product is protected by a U.S. patent.

Note that throughout this data sheet, multifunction pins, such as FD_A/GPIO_A0, are referred to either by the entire pin name or by a single function of the pin, for example, FD_A, when only that function is relevant.

1. Wide, input −3 dB bandwidth of 9 GHz supports direct radio frequency (RF) sampling of signals up to about 5 GHz.
2. Four integrated, wideband decimation filter and NCO blocks supporting multiband receivers.
3. Fast NCO switching enabled through GPIO pins.
4. A SPI controls various product features and functions to meet specific system requirements.
5. Programmable fast overrange detection and signal monitoring.
6. On-chip temperature dioide for system thermal management.
7. 12mm × 12mm 196-Lead BGA

Applications

• Diversity multiband, multimode digital receivers
• 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A
• Electronic test and measurement systems
• Phased array radar and electronic warfare
• DOCSIS 3.0 CMTS upstream receive paths
• HFC digital reverse path receivers

The ADRF5024 is a reflective, single-pole double-throw (SPDT) switch manufactured in the silicon process.

This switch operates from 100 MHz to 44 GHz with better than 1.7 dB of insertion loss and 35 dB of isolation. The ADRF5024 has an radio frequency (RF) input power handling capability of 27 dBm for both the through path and hot switching.

The ADRF5024 draws a low current of 14 µA on the positive supply of +3.3 V and 120 µA on negative supply of −3.3 V. The device employs complementary metal-oxide semiconductor (CMOS)-/low voltage transistor to transistor logic (LVTTL)compatible controls.

The ADRF5024 is pin-compatible with the ADRF5025, low frequency cutoff version, which operates from 9 kHz to 44 GHz.

The ADRF5024 RF ports are designed to match a characteristic impedance of 50 Ω. For ultrawideband products, impedance matching on the RF transmission lines can further optimize high frequency insertion loss and return loss characteristics. Refer to the Electrical Specifications section, Typical Performance Characteristics section, and Applications Information section for more details.

The ADRF5024 comes in a 2.25 mm × 2.25 mm, 12-terminal, RoHS-compliant, land grid array (LGA) package and can operate between −40°C to +105°C.

The ADRF5024-EP supports defense and aerospace applications (AQEC).

Applications

• Industrial scanners
• Test and instrumentation
• Cellular infrastructure: 5G mmWave
• Military radios, radars, electronic counter measures (ECMs)
• Microwave radios and very small aperture terminals (VSATs)

The HMC8192LG is a passive, wideband, inphase/quadrature (I/Q), monolithic microwave integrated circuit (MMIC) mixer that can be used either as an image rejection mixer for receiver operations or as a single-sideband upconverter for transmitter operations. With a radio frequency (RF) and local oscillator (LO) range of 20 GHz to 42 GHz, and an intermediate frequency (IF) bandwidth of dc to 5 GHz, the HMC8192LG is ideal for applications requiring a wide frequency range, excellent RF performance, and a simple design with fewer components and a small printed circuit board (PCB) footprint. A single HMC8192LG can replace multiple narrow-band mixers in a design.

The inherent I/Q architecture of the HMC8192LG offers excellent image rejection, eliminating the need for expensive filtering for unwanted sidebands. The mixer also provides excellent LO to RF and LO to IF isolation and reduces the effect of LO leakage to ensure signal integrity.

As a passive mixer, the HMC8192LG does not require any dc power sources. The HMC8192LG offers a lower noise figure compared to an active mixer, ensuring superior dynamic range for high performance and precision applications.

The HMC8192LG is fabricated on a gallium arsenide (GaAs), metal semiconductor field effect transistor (MESFET) process and uses Analog Devices, Inc., mixer cells and a 90° hybrid. The HMC8192LG is available in a compact, 4.00 mm × 4.00 mm, 25-terminal land grid array cavity (LGA_CAV) package and operates over a −40°C to +85°C temperature range. The evaluation board for the HMC8192LG, EV1HMC8192LG, is also available on the Analog Devices website.

Applications

• Test and measurement instrumentation
• Military, radar, aerospace, and defense applications
• Microwave point to point base stations

The ADF5356 allows implementation of fractional-N or integer N phase-locked loop (PLL) frequency synthesizers when used with an external loop filter and an external reference frequency. The wideband microwave VCO design permits frequency operation from 6.8 GHz to 13.6 GHz at one radio frequency (RF) output. A series of frequency dividers at another frequency output permits operation from 53.125 MHz to 6800 MHz.

The ADF5356 has an integrated VCO with a fundamental output frequency ranging from 3400 MHz to 6800 MHz. In addition, the VCO frequency is connected to divide by 1, 2, 4, 8, 16, 32, or 64 circuits that allow the user to generate RF output frequencies as low as 53.125 MHz. For applications that require isolation, the RF output stage can be muted. The mute function is both pin- and software-controllable.

Control of all on-chip registers is through a simple 3-wire interface. The ADF5356 operates with analog and digital power supplies ranging from 3.15 V to 3.45 V, with charge pump and VCO supplies from 4.75 V to 5.25 V. The ADF5356 also contains hardware and software power-down modes.

Applications

• Wireless infrastructure (LTE, W-CDMA, TD-SCDMA, WiMAX, GSM, PCS, DCS)
• Point to point and point to multipoint microwave links
• Satellites and very small aperture terminals (VSATs)
• Test equipment and instrumentation
• Clock generation

The circuit shown in Figure 1 is an accurate 40 GHz, microwave power meter with a 45 dB range that requires only two components. The RF detector has an innovative detector cell using Schottky diodes followed by an analog linearization circuit. A low power, 12-bit, 1 MSPS analog-to-digital converter (ADC) provides a digital output on a serial peripheral interface (SPI) port.

A simple calibration routine is run before measurement operation, at the particular RF frequency of interest. The user can then operate the system in measurement mode. When in measurement mode, the CN-0366 Evaluation Software displays the calibrated RF input power that is applied at the input of the detector in units of dBm.

The total power dissipation of this circuit is less than 9 mW on a single 5 V supply.

The PLL circuit shown in Figure 1 uses a 13 GHz Fractional-N synthesizer, wideband active loop filter and VCO, and has a phase settling time of less than 5 μs to within 5° for a 200 MHz frequency jump.

The performance is achieved using an active loop filter with 2.4 MHz bandwidth. This wide bandwidth loop filter is achievable because of the ADF4159 phase-frequency detector (PFD) maximum frequency of 110 MHz; and the AD8065 op amp high gain-bandwidth product of 145 MHz.

The AD8065 op amp used in the active filter can operate on a 24 V supply voltage that allows control of most wideband VCOs having tuning voltages from 0 V to 18 V.

This circuit is a complete implementation of a low noise microwave fractional-N PLL using the ADF4156 as the core fractional-N PLL device. The ADF5001 external prescaler is used to extend the frequency range of the PLL up to 18 GHz. An ultralow noise OP184 op amp with appropriate biasing and filtering is used to drive a microwave VCO to implement a complete low noise PLL at 12 GHz with a measured integrated phase noise of 0.35 ps rms. This function is typically used to generate the local oscillator frequency (LO) for applications such as microwave point-to-point systems, test and measurement equipment, automotive radar, and military applications.

The circuit block diagram shown in Figure 1 is a low phase noise translation loop synthesizer (also known as an offset loop). This circuit translates the lower 100 MHz reference frequency of the ADF4002 phase locked loop (PLL) up to a higher frequency range of 5.0 GHz to 5.4 GHz, as determined by the frequency of the local oscillator (LO).

The translation loop synthesizer has very low phase noise (<50 fs) in contrast to a synthesizer using only a PLL. The low phase noise is because of the very low N value used by the ADF4002 integer-N PLL, which controls the voltage controlled oscillator (VCO). In this example, the ADF4002 phase frequency detector (PFD) runs at 100 MHz, and N = 1, yielding phase noise performance that is not limited by the N value of the PLL.

• General purpose design suitable for any software-designed radio application
• MIMO radio
• Transmit beamforming and receive angle of arrival detection
• Point to point communication systems
• Femtocell/picocell/microcell base stations

The AD-FMCOMMS6-EBZ eval board is a 400MHz to 4.4GHz receiver based on the AD9652 dual 16bit analog to digital converter, the ADL5566 High Dynamic Range RF/IF Dual Differential Amplifier and the ADL5380 quadrature demodulator.

This is an I and Q demodulation approach to direct convert (also known as a homodyne or zero IF) receiver architecture. Direct conversion radios perform just one frequency translation compared to a super-heterodyne receiver that can perform several frequency translations. One frequency translation is advantageous because it:

• Reduces receiver complexity and the number of stages needed, increasing performance and reducing power consumption
• Avoids image rejection issues and unwanted mixing

This topology will provide image rejection and early implementation of the differential signal environment. There is an amplification stage to maintain the full-scale input to the ACD. The local oscillator and ADC clock are on board and share the same reference signal prevent smearing. The form factor is VITA57 compliant and all of the DC power is routed from the data capture board through an FMC connector. This evaluation board demonstrates a high performance receiver signal chain aimed at military and commercial radar using “commercial off the shelf” (COTS) components. The overall circuit has a bandwidth of 220MHz with a pass band flatness of +/_ 1.0 dB. The SNR and SFDR measured at an IF of 145MHz are 64dB and 75dBc, respectively.