Features and Benefits
- Dual receivers
- Maximum Receiver BW: 200 MHz
- Fully integrated, fractional-N, RF synthesizers
- Fully integrated clock synthesizer
- Multichip phase synchronization for RF LO and baseband clocks
- JESD204B datapath interface
- Tuneable range: 75 MHz to 6000 MHz
The receive path consists of two independent, wide bandwidth (BW), direct conversion receivers with state-of-the-art dynamic range. The complete receive subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. RF front-end control and several auxiliary functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) for the power amplifier (PA) are also integrated.
In addition to automatic gain control (AGC), the ADRV9008-1 also features flexible external gain control modes, allowing significant flexibility in setting system level gain dynamically.
The received signals are digitized with a set of four high dynamic range, continuous time, sigma-delta (Σ-Δ) ADCs that provide inherent antialiasing. The combination of the direct conversion architecture, which does not suffer from out of band image mixing, and the lack of aliasing relaxes the requirements of the RF filters compared to traditional intermediate frequency (IF) receivers.
The fully integrated phase-locked loop (PLL) provides high per-formance, low power, fractional-N, RF synthesis for the receiver signal paths. An additional synthesizer generates the clocks needed for the converters, digital circuits, and the serial interface. A multi-chip synchronization mechanism synchronizes the phase of the RF local oscillator (LO) and baseband clocks between multiple ADRV9008-1 chips. Precautions are taken to provide the isolation required in high performance base station applications. All voltage controlled oscillators (VCOs) and loop filter components are integrated.
The high speed JESD204B interface supports up to 12.288 Gbps lane rates, resulting in two lanes per transmitter and a single lane per receiver in the widest bandwidth mode. The interface also supports interleaved mode for lower bandwidths, reducing the total number of high speed data interface lanes to one. Both fixed and floating point data formats are supported. The floating point format allows internal AGC to be invisible to the demodulator device.
The core of the ADRV9008-1 can be powered directly from 1.3 V and 1.8 V regulators and is controlled via a standard 4-wire serial port. Comprehensive power-down modes are included to mini-mize power consumption during normal use. The ADRV9008-1 is packaged in a 12 mm × 12 mm, 196-ball chip scale ball grid array (CSP_BGA).
- 3G, 4G, and 5G FDD, macrocell base stations
- Wide band active antenna systems
- Massive multiple input, multiple output (MIMO)
- Phased array radar
- Electronic warfare
- Military communications
- Portable test equipment
Markets and Technologies
Product Lifecycle Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (1)
The ADRV9009-W/PCBZ is a radio card designed to showcase the ADRV9009, the widest bandwidth, highest performance RF integrated transceiver. The radio card provides a single 2x2 transceiver platform for device evaluation and rapid prototyping of radio solutions. All peripherals necessary for the radio card to operate including a high efficiency switcher only power supply solution, and a high performance clocking solution are populated on the board. The ADRV9009-W/PCBZ is a single-chip TDD solution of dual receivers, dual transmitters with observation receiver.
The ADRV9009-W/PCBZ operates over a wide tuning range 75MHz – 6GHz, however the RF performance is tempered by the very wide band front end match. This board is primarily intended for system investigation and bringing up various waveforms from a software team before custom hardware is complete. The objective being for designers to see waveforms, but not being concerned about the last 1dB or 1% EVM of performance.
The ADRV9008-1W/PCBZ is an evaluation kit to showcase the ADRV9008-1, offering dual receivers over a tuning range 75MHz – 6GHz. The ADRV9008-2W/PCBZ is an evaluation kit to showcase the ADRV9008-2, offering dual transmitters with observation receiver over a tuning range 75MHz – 6GHz.
ADRV9008/ADRV9009 Evaluation and Prototyping Platforms
ADI provides a full set of software and hardware tools for evaluation, prototyping and reference design. The following table outlines the available hardware and software tools.
|Carrier Boards||Software & Driver|
|Evaluation Platform||Evaluation Software:
Features & Benefits
- Complete Radio Card for evaluation
- ADRV9009-W/PCBZ: Evaluation kit for ADRV9009 (Dual RF Rx/Tx/Orx Evaluation Board)
- ADRV9008-1W/PCBZ: Evaluation kit for ADRV9008-1 (Dual RF Rx Evaluation Board)
- ADRV9008-2W/PCBZ: Evaluation kit for ADRV9008-2 (Dual RF Tx/Orx Evaluation Board)
- Wide band RF operation over 75MHz - 6GHz frequency range
- Complete with high efficiency power supply solution and clocking solution
- FMC connector to Xilinx motherboard (EVAL-TPG-ZYNQ3)
- Powered from single FMC connector
- Includes schematics, layout, BOM, HDL, drivers and application software
Software & Systems Requirements
Wideband RF Transceiver Evaluation Software
Product Selection Guide (1)
Solutions Bulletins & Brochures (1)
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.
Support & Discussions
Sample & Buy
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