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ADRV9008-1: Integrated Dual RF Receiver Data Sheet (Rev. 0)6/8/2018PDF2 M
Overview
Features and Benefits
- Dual receivers
- Maximum Receiver BW: 200 MHz
- Fully integrated, fractional-N, RF synthesizers
- Fully integrated clock synthesizer
- Multichip phase synchronization for RF LO and baseband clocks
- JESD204B datapath interface
- Tuneable range: 75 MHz to 6000 MHz
Product Details
The receive path consists of two independent, wide bandwidth (BW), direct conversion receivers with state-of-the-art dynamic range. The complete receive subsystem includes automatic and manual attenuation control, dc offset correction, quadrature error correction (QEC), and digital filtering, eliminating the need for these functions in the digital baseband. RF front-end control and several auxiliary functions such as analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and general-purpose input/outputs (GPIOs) for the power amplifier (PA) are also integrated.
In addition to automatic gain control (AGC), the ADRV9008-1 also features flexible external gain control modes, allowing significant flexibility in setting system level gain dynamically.
The received signals are digitized with a set of four high dynamic range, continuous time, sigma-delta (Σ-Δ) ADCs that provide inherent antialiasing. The combination of the direct conversion architecture, which does not suffer from out of band image mixing, and the lack of aliasing relaxes the requirements of the RF filters compared to traditional intermediate frequency (IF) receivers.
The fully integrated phase-locked loop (PLL) provides high per-formance, low power, fractional-N, RF synthesis for the receiver signal paths. An additional synthesizer generates the clocks needed for the converters, digital circuits, and the serial interface. A multi-chip synchronization mechanism synchronizes the phase of the RF local oscillator (LO) and baseband clocks between multiple ADRV9008-1 chips. Precautions are taken to provide the isolation required in high performance base station applications. All voltage controlled oscillators (VCOs) and loop filter components are integrated.
The high speed JESD204B interface supports up to 12.288 Gbps lane rates, resulting in two lanes per transmitter and a single lane per receiver in the widest bandwidth mode. The interface also supports interleaved mode for lower bandwidths, reducing the total number of high speed data interface lanes to one. Both fixed and floating point data formats are supported. The floating point format allows internal AGC to be invisible to the demodulator device.
The core of the ADRV9008-1 can be powered directly from 1.3 V and 1.8 V regulators and is controlled via a standard 4-wire serial port. Comprehensive power-down modes are included to mini-mize power consumption during normal use. The ADRV9008-1 is packaged in a 12 mm × 12 mm, 196-ball chip scale ball grid array (CSP_BGA).
Applications
- 3G, 4G, and 5G FDD, macrocell base stations
- Wide band active antenna systems
- Massive multiple input, multiple output (MIMO)
- Phased array radar
- Electronic warfare
- Military communications
- Portable test equipment
Product Categories
Markets and Technologies
Product Lifecycle
Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (1)
Documentation & Resources
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RF, Microwave, and Millimeter Wave Product Selection Guide7/13/2018PDF9M
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Radioverse Technology and Radio Design Ecosystem Brochure7/22/2020PDF3 M
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RadioVerse ADRV9009 Overview10/15/2018
Software & Systems Requirements
Evaluation Software
Wideband RF Transceiver Evaluation Software
The Evaluation kit offers several software drivers for evaluation and rapid prototyping as well as design tool options to aid in simulation and filter design.
Design Resources
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.View our quality and reliability program and certifications for more information.
| Part Number | Material Declaration | Reliability Data | Pin/Package Drawing | CAD Symbols, Footprints & 3D Models |
|---|---|---|---|---|
| ADRV9008BBCZ-1 | Material Declaration | Reliability Data | 196-Ball CSPBGA (12mm x 12mm) | |
| ADRV9008BBCZ-1REEL | Material Declaration | Reliability Data | 196-Ball CSPBGA (12mm x 12mm) | |
| Wafer Fabrication Data |
Support & Discussions
ADRV9008-1 Discussions
ADRV9009: Using FSM driver for multiple topologies with same clock source (AD9528)
21 week(s) ago in FPGA Reference Designs
How to use two adrv9008 on single ZCU102 board?
23 week(s) ago in FPGA Reference Designs
Sample & Buy
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Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.