The ADRV9040 is a highly integrated, system on chip (SoC) radio
frequency (RF) agile transceiver with integrated digital front end
(DFE). The SoC contains eight transmitters, two observation receivers
to monitor transmitter channels, eight receivers, integrated LO
and clock synthesizers, and digital signal processing functions. The
SoC meets the high radio performance and low power consumption
demanded by cellular infrastructure applications including small cell
base-station radios, macro 3G/4G/5G systems, and massive MIMO
base stations.
The receiver and transmitter signal paths use a zero-IF (ZIF)
architecture that provides wide bandwidth with dynamic range suitable
for contiguous and non-contiguous multi-carrier base-station
applications. The ZIF architecture has the benefits of low power
plus RF frequency and bandwidth agility. The lack of aliases and
out-of-band images eliminate anti-aliasing and image filters. This
reduces both system size and cost, also making band independent
solutions possible.
The device also includes two wide-bandwidth observation path
receiver subsystems to monitor transmitter outputs. This SoC subsystem
includes automatic and manual attenuation control, DC
offset correction, quadrature error correction (QEC), and digital
filtering. GPIOs that provide an array of digital control options are
also integrated.
Multi-band capability is enabled by additional LO dividers and
wideband operation. This allows four individuals band profiles within
the tunable range, so maximizing use case flexibility.
The SoC has fully integrated DFE functionality, which includes
carrier digital up/down conversion (CDUC and CDDC), crest factor
reduction (CFR), digital predistortion (DPD), closed-loop gain control
(CLGC) and voltage standing wave ratio (VSWR) monitor.
The CDUC feature of the ADRV9040 filters and places individual
component carriers within the band of interest. The CDDC feature,
with its eight parallel paths, processes each carrier individually
before sending over the serial data interface.
The CDUC and CDDC reduce serialization/deserialization
(SERDES) interface data rates in non-contiguous carrier configurations.
This integration also reduces power compared to an equivalent
FPGA based implementation.
The CFR engine of the ADRV9040 reduces the peak-to-average
ratio (PAR) of the input signal, which enables higher efficiency
transmit line ups while reducing the processing load on baseband
processors.
The SoC also contains a fully integrated DPD engine for use in
power amplifier linearization. The DPD enables the high-efficiency
power amplifiers, which reduce the power consumption of base-station
radios and the number of SERDES lanes interfacing with
baseband processors. The DPD engine incorporates a dedicated
long-term DPD (LT-DPD) block, which provides the support for GaN
power amplifiers. The ADRV9040 tackles charge-trapping property
of GaN power amplifiers with its LT-DPD block, hence improving
the emissions and error vector magnitude (EVM). The SoC includes
an ARM Cortex-A55 quad core processor to independently serve
DPD, CLGC, and VSWR monitor features. The dedicated processor,
together with the DPD engine, provides industry leading DPD
performance.
The serial data interface consists of eight serializer and deserializer
lanes. The interface supports the JESD204C standards, and both
fixed and floating-point data formats are supported. The floatingpoint
format allows internal automatic gain control (AGC) to be
transparent to the baseband processor.
The ADRV9040 is powered directly from 0.8 V, 1.0 V, and 1.8 V
regulators and is controlled through a standard SPI serial port. The
comprehensive power-down modes are included to minimize the
power consumption in normal use. The device is packaged in a 27
mm × 20 mm, 736-ball grid array.
Applications
- 3G/4G/5G time division duplex (TDD)/frequency division duplex
(FDD) small cell, massive MIMO, and macro base stations
