New Content (1)
Features and Benefits
- Integrated dual-channel RF front end
- 2-stage LNA and high power silicon SPDT switch
- On-chip bias and matching
- Single-supply operation
- High power handling at TCASE = 105°C
- LTE average power (9 dB PAR) full lifetime: 43 dBm
- High gain mode: 36 dB typical at 3.6 GHz
- Low gain mode: 17 dB typical at 3.6 GHz
- Low noise figure
- High gain mode: 1.05 dB typical at 3.6 GHz
- Low gain mode: 1.05 dB typical at 3.6 GHz
- High isolation
- RXOUT-CHA and RXOUT-CHB: 47 dB typical
- TERM-CHA and TERM-CHB: 75 dB typical
- Low insertion loss: 0.5 dB typical at 3.6 GHz
- High OIP3: 35 dBm typical
- Power-down mode and low gain mode
- Low supply current
- High gain mode: 95 mA typical at 5 V
- Low gain mode: 48 mA typical at 5 V
- Power-down mode: 13 mA typical at 5 V
- Positive logic control
- 6 mm × 6 mm, 40-lead LFCSP package
- Pin compatible with the ADRF5515 and the ADRF5519, and the 10 W versions, ADRF5545A and ADRF5549
The ADRF5515A is a dual-channel, integrated RF, front-end, multichip module designed for time division duplexing (TDD) applications. The device operates from 3.3 GHz to 4.0 GHz. The ADRF5515A is configured in dual channels with a cascading, two-stage low noise amplifier (LNA) and a high-power silicon singlepole, double-throw (SPDT) switch.
In high gain mode, the cascaded two-stage LNA and switch offer a low noise figure of 1.05 dB and a high gain of 36 dB at 3.6 GHz, with an output third-order intercept (OIP3) point of 35 dBm (typical). In low gain mode, one stage of the two-stage LNA is in bypass, providing 17 dB of gain at a lower current of 48 mA. In power-down mode, the LNAs are turned off and the device draws 13 mA.
In transmit operation, when RF inputs are connected to a termination pin (TERM-CHA or TERM-CHB), the switch provides low insertion loss of 0.5 dB and handles long-term evolution (LTE) average power (9 dB peak to average ratio (PAR)) of 43 dBm for full lifetime operation.
The device comes in an RoHS-compliant, compact, 6 mm × 6 mm, 40-lead lead frame chip scale package (LFCSP).
Product Lifecycle Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (1)
The ADRF5515A is an integrated, dual-channel, 3.3 GHz to 4.0 GHz, 20 W receiver front end ideally suited for time division duplexing (TDD) wireless infrastructure applications. The ADRF5515A consists of a high power switch and a two-stage low noise amplifier (LNA) on each channel.
The user guide describes the ADRF5515A-EVALZ, designed to easily evaluate the features and performance of the ADRF5515A. A photograph of the ADRF5515A-EVALZ is shown in Figure 1 of the user guide.
The ADRF5515A data sheet provides full specifications for the ADRF5515A. Consult the ADRF5515A data sheet in conjunction with the user guide when using the ADRF5515A-EVALZ.
Tools & Simulations
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.
Sample & Buy
The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.