Overview
Features and Benefits
- Dual transmitters
- Dual input shared observation Rx
- Maximum tunable Tx synthesis BW: 450 MHz
- Maximum observation Rx BW: 450 MHz
- Fully integrated fractional-N RF synthesizers
- Fully integrated clock synthesizer
- Multi-chip phase synchronization for RF LO and baseband clocks
- JESD204B datapath interface
- Tuning range: 75 MHz to 6000 MHz
Product Details
The ADRV9008-2 is a highly integrated, RF agile transmit subsystem offering dual channel transmitters, observation path receiver, integrated synthesizers, and digital signal processing functions. The IC delivers a versatile combination of high performance and low power consumption demanded by 2G, 3G and 4G macro-cell base stations, and active antenna, applications.
The transmitters use an innovative direct conversion modulator that achieves multi-carrier macro-base-station quality performance and very low power. In 3G/4G mode, the maximum large-signal bandwidth is 200MHz. In MC-GSM mode, which has higher in-band SFDR, the maximum large-signal bandwidth is 75MHz.
The observation path consists of a wide bandwidth direct-conversion receiver with state-of-the-art dynamic range. The complete receive subsystem includes dc offset correction, quadrature correction, and digital filtering thus eliminating the need for these functions in the digital baseband. Several auxiliary functions such as ADCs, DACs, and GPIOs for PA and RF-front-end control are also integrated.
The fully integrated phase locked loops (PLLs) provide high performance, low power fractional-N RF frequency synthesis for the transmitter and receiver sections. An additional synthesizer is used to generate the clocks needed for the converters, digital circuits, and the serial interface. Special precautions have been taken to provide the isolation demanded in high performance base station applications. All VCO and loop filter components are integrated.
The high-speed JESD204B interface supports up to 12.288 Gbps lane rates resulting in two lanes per transmitter in the widest bandwidth mode and two lanes for the observation path receiver in the widest bandwidth mode.
The core of the ADRV9008-2 can be powered directly from 1.3 V and 1.8 V regulators and is controlled via a standard 4 wire serial port. Comprehensive power-down modes are included to minimize power consumption in normal use. The ADRV9008-2 is packaged in a 12mm × 12 mm, 196-ball chip scale ball grid array (CSP_BGA).
Product Lifecycle
Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (1)
Documentation & Resources
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RadioVerse ADRV9009 Overview10/15/2018
Software & Systems Requirements
Evaluation Software
Wideband RF Transceiver Evaluation Software
Design Resources
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.View our quality and reliability program and certifications for more information.
Part Number | Material Declaration | Reliability Data | Pin/Package Drawing | CAD Symbols, Footprints & 3D Models |
---|---|---|---|---|
ADRV9008BBCZ-2 | Material Declaration | Reliability Data | 196-Ball CSPBGA (12mm x 12mm) | |
ADRV9008BBCZ-2REEL | Material Declaration | Reliability Data | 196-Ball CSPBGA (12mm x 12mm) | |
Wafer Fabrication Data |
Support & Discussions
ADRV9008-2 Discussions
Sample & Buy
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Buy Now Pricing
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List Pricing
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Evaluation Boards
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Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.