ADRV9042

预发布

8T8R SoC with DFE, 400 MHz iBW RF Transceiver

数据手册 (Rev. C) 产品选型表
产品技术资料帮助

ADI公司所提供的资料均视为准确、可靠。但本公司不为用户在应用过程中侵犯任何专利权或第三方权利承担任何责任。技术指标的修改不再另行通知。本公司既没有含蓄的允许，也不允许借用ADI公司的专利或专利权的名义。本文出现的商标和注册商标所有权分别属于相应的公司。
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产品详情

  • Highly integrated transceiver
  • 8 transmit (Tx), 8 receive (Rx), and 2 observation receivers (ORx)
  • LO tuning range: 600 MHz to 7125 MHz
  • RF range: 500 MHz to 7455 MHz1
  • Zero-IF architecture reduces system size, weight, and power (SWaP)
    • Initial and run time calibrations maintain high performance
  • Dual fully integrated fractional-N RF synthesizers
  • Dual external LO inputs supporting operation up to 6 GHz.
  • Multichip phase synchronization for all local oscillator (LO) and baseband clocks
  • Single and multiband (N × 2T2R/4T4R) capability
  • 4 individual band profiles within tunable range (band profiles define bandwidth and aggregate sampling rate of a channel)
  • Fully integrated DPD supporting up to 400 MHz iBW/OBW
  • Supports up to 660 MHz instantaneous BW, 400 MHz occupied BW on RF front end with DFE enabled
  • Supports up to 400 MHz instantaneous/occupied BW with DFE disabled
  • Supports JESD204B and JESD204C digital interface
  • Simplifying thermal and power consumption challenges
  • 10.44 W power consumption for the TDD mode, full DFE features enabled use case with 100 MHz iBW/OBW2
  • 125°C maximum junction temperature for intermittent operation, 110°C for continuous (operating lifetime impact at >110°C can be offset by operation at <110°C based on acceleration factors)
  • Fully integrated DFE (DPD, CDUC, CDDC, and CFR) engine reduces FPGA resources, halves SERDES lane rate, and simplifies designs
    • DPD adaptation engine for power amplifier linearization
    • CDUC/CDDC—maximum of 8 component carriers (CCs) per each transmitter/receiver channel
    • Multistage CFR engine
  • Low power monitor and sleep modes
ADRV9042
8T8R SoC with DFE, 400 MHz iBW RF Transceiver
ADRV9042 Functional Block Diagram ADRV9042 Pin Configuration ADRV9042 Chip Illustration
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参考资料

数据手册 1

用户手册 1

应用笔记 7

技术文章 4

产品亮点 1

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软件资源

API Device Drivers 1

Device Application Programming Interface (API) C code drivers provided as reference code allows the user to quickly configure the product using high-level function calls. The library acts as an abstraction layer between the application and the hardware. The API is developed in C99 to ensure agnostic processor and operating system integration. Customers can port this application layer code to their embedded systems/ Baseband Processor by integrating their platform-specific code base to the API HAL layer. To request this software package, go to the Software Request Form signed in with your MyAnalog account and under “Target Technology option - select “Wireless Communications" and choose processor/SOC as "ADRV9040 or ADRV9044" , select the check box as well and submit the form. You will receive an email notification with a link for software download.

工具及仿真模型

SDR Integrated Transceiver Design Resources

This site contains the device documentation packages for the SDR Integrated Transceivers including user guides, IBIS models, and PCB files.

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ADIsimRF

ADIsimRF是一款简单易用的RF信号链计算工具。可以计算和导出多达50级的信号链级联增益、噪声、失真和功耗并绘制其曲线。ADIsimRF还包括丰富的ADI射频和混合信号元件的器件模型数据库。

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