製品概要

機能と利点

  • Flexible reconfigurable common platform design
    • Supports single-, dua-l, and quad-band
    • Datapaths and DSP blocks are fully bypassable
    • On-chip PLL with multichip synchronization
      • External RF clock input option for off-chip PLL
      • Supports clock input frequencies up to 12 GHz
  • Maximum ADC sample rate up to 4 GSPS
    • Maximum data rate up to 4 GSPS using JESD204C
    • 8 GHz analog input bandwidth (−3 dB)
  • ADC ac performance at 4 GSPS
    • Differential input voltage: 1.4 V p-p
    • Noise density: −151.5 dBFS/Hz
    • HD2: −69 dBFS at 2.7 GHz (AIN at −1 dBFS)
    • HD3: −76 dBFS at 2.7 GHz (AIN at −1 dBFS)
    • Worst other (excluding HD2 and HD3): −79 dBFS at 2.7 GHz
  • Auxiliary features
    • Phase coherent fast frequency hopping
    • ADC clock driver with selectable divide ratios
    • On-chip temperature monitoring unit
    • Flexible GPIOx pins
  • Versatile digital features
    • Selectable decimation filters
    • Configurable DDCs
      • 8 fine complex DDCs and 4 coarse complex DDCs
      • 48-bit NCO per DDC
    • Programmable 192-tap PFIR filter for receive equalization
      • Supports 4 different profile settings loaded via GPIO
    • Programmable delay per datapath
    • Receive AGC support
      • Fast detect with low latency for fast AGC control
      • Signal monitor for slow AGC control
      • Dedicated AGC support pins
  • SERDES JESD204B/JESD204C interface, 8 lanes up to 24.75 Gbps
    • 8 lanes per ADCs
    • 8 lanes JESD204B/JESD204C Tx (JTx)
    • Supports real or complex digital data (8-, 12-, 16-, or 24-bit)
  • 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch

製品概要

The AD9209 is a quad, 12-bit, 4 GSPS analog-to-digital converter (ADC). The ADC input features an on-chip wideband buffer with overload protection. This device is designed to support applications capable of direct sampling wideband signals up to 8 GHz. An on-chip, low phase noise, phase-locked loop (PLL) clock synthesizer is available to generate the ADC sampling clock, simplifying the printed circuit board (PCB) distribution of a high frequency clock signal. A clock output buffer is available to transmit the ADC sampling clock to other devices.

The quad ADC cores have code error rates (CER) better than 1 × 10−20. Low latency fast detection and signal monitoring are available for automatic gain control (AGC) purposes. A flexible 192-tap programmable finite impulse response filter (PFIR) is avail-able for digital filtering and/or equalization. Programmable integer and fractional delay blocks support compensation for analog delay mismatches.

The digital signal processing (DSP) block consisting of two coarse digital down converters (DDCs) and four fine DDCs per pair of ADCs. Each ADC can operate with one or two main DDC stages in support of multiband applications. The four additional fine DDC stages are available to support up to four bands per ADC The 48-bit numerically controlled oscillators (NCOs) associated with each DDC support fast frequency hopping (FFH) while maintaining synchronization with up to 16 unique frequency assignments selected via the general-purpose input and output (GPIOx) pins or the serial port interface (SPI).

The AD9209 supports one or two JTx links that can be configured for either JESD204B or JESD204C subclass operation, thus allowing for different datapath configurations for each ADC. Multidevice synchronization is supported through the SYSREF± input pins.

APPLICATIONS

  • Wireless communications infrastructure
  • Microwave point-to-point, E-band, and 5G mm wave
  • Broadband communications systems
  • DOCSIS 3.1 and 4.0 CMTS
  • Phased array radar and electronic warfare
  • Electronic test and measurement systems

製品ライフサイクル icon-recommended 発売前

新たに発売予定の製品です。技術的な検証が継続中の場合もあります。数量が限られており、設計仕様は量産開始前に変更されることがあります。

評価キット (3)

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設計ツール

Companion Transport Layer RTL Code Generator Tool (Rev. 1.0)

This command line executable tool generates a Verilog module which implements the JESD204 receive transport layer. The user specifies in a configuration file one or more modes to be supported by the transport layer module. These modes are defined as a set of JESD204 parameter values: L, M, F, S, N', and CF. The transport layer converts JESD204 lane data output from a JESD204 link layer IP to a data bus with a fixed width, containing interleaved virtual converter samples. Both JESD204B and JESD204C link layers are supported.

JESD204x Frame Mapping Table Generator

The JESD204x Frame Mapping Table Generator tool consists of two Windows executables that will allow the user to input any valid combination of JESD204x parameters (L, M, F, S, NP) in order to output a .csv file that illustrates the frame mapping of the JESD204x mode in table format. There is an executable that allows the user to input a single JESD204x mode and another, that allows the user to input the parameters for multiple JESD204x modes in a specified .csv format in order to output a .csv file that illustrates the frame mapping of each of the JESD204x modes that were input into separate tables.

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設計リソース

ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well.  "Zero defects" for shipped products is always our goal.

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価格は1個当たりの米ドルで、米国内における販売価格(FOB)で表示されておりますので、予算のためにのみご使用いただけます。 また、その価格は変更されることがあります。米国以外のお客様への価格は、輸送費、各国の税金、手数料、為替レートにより決定されます。価格・納期等の詳細情報については、弊社正規販売代理店または担当営業にお問い合わせください。なお、 評価用ボードおよび評価用キットの表示価格は1個構成としての価格です。