AD9634
12-Bit, 170 MSPS/210 MSPS/250 MSPS, 1.8 V Analog-to-Digital Converter
Show More
Not the part you were looking for?
Ask a Question
Submit your question below and we will return the best answer from ADI’s knowledge database:
Search
Other places you can find help
Support
Analog Devices Support Portal is a one-stop shop to answer all your ADI questions.
Visit the ADI Support Page
Features
- SNR = 69.7 dBFS at 185 MHz AIN and 250 MSPS
- SFDR = 87 dBc at 185 MHz AIN and 250 MSPS
- −150.6 dBFS/Hz input noise at 185 MHz, −1 dBFS AIN and 250 MSPS
- Total Power consumption: 360 @ 250 MSPS
- 1.8 V supply voltages
- LVDS (ANSI-644 levels) outputs
- Integer 1-to-8 input clock divider (625 MHz maximum input)
- Sample rates of up to 250 MSPS
- IF sampling frequencies of up to 350 MHz
- Internal ADC voltage reference
- Flexible analog input range 1.4 V p-p to 2.0 V p-p (1.75 V p-p nominal)
- See data sheet for additional features
.svg?rev=fd385c90e2cf4716ae9a8c8d20e6b8e3&la=en&h=24&w=24&hash=A302DF48F94BAAA11877AF223F27157A){kind=icon}
The AD9634 is a 12-bit, analog-to-digital converter (ADC) with sampling speeds of up to 250 MSPS. The AD9634 is designed to support communications applications where low cost, small size, wide bandwidth, and versatility are desired.
The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features wide bandwidth inputs that can support a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) is provided to compensate for variations in the ADC clock duty cycle, allowing the converter to maintain excellent performance.
The ADC output data are routed directly to the external 12-bit LVDS output port.
Flexible power-down options allow significant power savings, when desired.
Programming for setup and control is accomplished using a 3-wire, SPI-compatible serial interface.
The AD9634 is available in a 32-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent.
PRODUCT HIGHLIGHTS
- Integrated 12-bit, 170 MSPS/210 MSPS/250 MSPS ADC.
- Fast overrange and threshold detect.
- Proprietary differential input maintains excellent SNR performance for input frequencies up to 350 MHz.
- 3-pin, 1.8V SPI port for register programming and readback.
- Pin compatibility with the AD9642, allowing a simple migration up to 14 bits, and with the AD6672.
APPLICATIONS
- Communications
- Diversity radio systems
- Multimode digital receivers (3G)
TD-SCDMA, WiMax, WCDMA, CDMA2000, GSM, EDGE, LTE - I/Q demodulation systems
- Smart antenna systems
- General-purpose software radios
- Ultrasound equipment
- Broadband data applications
Ask a Question
Submit your question below and we will return the best answer from ADI’s knowledge database:
Search
Other places you can find help
Support
Analog Devices Support Portal is a one-stop shop to answer all your ADI questions.
Visit the ADI Support Page
{{modalTitle}}
{{modalDescription}}
{{dropdownTitle}}
- {{defaultSelectedText}} {{#each projectNames}}
- {{name}} {{/each}} {{#if newProjectText}}
-
{{newProjectText}}
{{/if}}
{{newProjectTitle}}
{{projectNameErrorText}}
AD9634
Documentation
Filters
1 Applied
-
All
-
User Guide
-
Evaluation Design File
-
Data Sheet
-
Application Note
-
All
-
English
-
Chinese
-
Japanese
Data Sheet
2
User Guide
3
165 kB
165 kB
Evaluation Design File
4
xls
xls
562 kB
Application Note
33
969 kB
1559 kB
1606 kB
HTML
HTML
HTML
HTML
HTML
HTML
HTML
HTML
HTML
HTML
HTML
HTML
Documentation
Data Sheet 1
User Guide 2
Application Note 12
AN-807: Multicarrier WCDMA Feasibility (Rev.0)
AN-803: Pin Compatible High Speed ADCs Simplify Design Tasks (Rev.0)
AN-808: Multicarrier CDMA2000 Feasibility (Rev.0)
AN-282: Fundamentals of Sampled Data Systems
AN-878: High Speed ADC SPI Control Software (Rev.A)
AN-827: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs (Rev.0)
AN-737: How ADIsimADC Models an ADC (Rev.B)
AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev.0)
AN-835: Understanding High Speed ADC Testing and Evaluation
AN-1142: Techniques for High Speed ADC PCB Layout
AN-905: VisualAnalog™ Converter Evaluation Tool Version 1.0 User Manual
AN-935: Designing an ADC Transformer-Coupled Front End
Evaluation Design File 2
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| AD9634BCPZ-170 |
32-Lead LFCSP (5mm x 5mm x 0.75mm w/ EP)
|
|
|
| AD9634BCPZ-210 |
32-Lead LFCSP (5mm x 5mm x 0.75mm w/ EP)
|
|
|
| AD9634BCPZ-250 |
32-Lead LFCSP (5mm x 5mm x 0.75mm w/ EP)
|
|
|
| AD9634BCPZRL7-170 |
32-Lead LFCSP (5mm x 5mm x 0.75mm w/ EP)
|
|
|
| AD9634BCPZRL7-210 |
32-Lead LFCSP (5mm x 5mm x 0.75mm w/ EP)
|
|
|
| AD9634BCPZRL7-250 |
32-Lead LFCSP (5mm x 5mm x 0.75mm w/ EP)
|
|
- AD9634BCPZ-170
- Pin/Package Drawing
-
32-Lead LFCSP (5mm x 5mm x 0.75mm w/ EP)
- Documentation
-
HTML
Material Declaration
-
HTML
Reliablity Data
- CAD Symbols, Footprints, and 3D Models
-
Ultra Librarian
-
SamacSys
- AD9634BCPZ-210
- Pin/Package Drawing
-
32-Lead LFCSP (5mm x 5mm x 0.75mm w/ EP)
- Documentation
-
HTML
Material Declaration
-
HTML
Reliablity Data
- CAD Symbols, Footprints, and 3D Models
-
Ultra Librarian
-
SamacSys
- AD9634BCPZ-250
- Pin/Package Drawing
-
32-Lead LFCSP (5mm x 5mm x 0.75mm w/ EP)
- Documentation
-
HTML
Material Declaration
-
HTML
Reliablity Data
- CAD Symbols, Footprints, and 3D Models
-
Ultra Librarian
-
SamacSys
- AD9634BCPZRL7-170
- Pin/Package Drawing
-
32-Lead LFCSP (5mm x 5mm x 0.75mm w/ EP)
- Documentation
-
HTML
Material Declaration
-
HTML
Reliablity Data
- CAD Symbols, Footprints, and 3D Models
-
Ultra Librarian
-
SamacSys
- AD9634BCPZRL7-210
- Pin/Package Drawing
-
32-Lead LFCSP (5mm x 5mm x 0.75mm w/ EP)
- Documentation
-
HTML
Material Declaration
-
HTML
Reliablity Data
- CAD Symbols, Footprints, and 3D Models
-
Ultra Librarian
-
SamacSys
- AD9634BCPZRL7-250
- Pin/Package Drawing
-
32-Lead LFCSP (5mm x 5mm x 0.75mm w/ EP)
- Documentation
-
HTML
Material Declaration
-
HTML
Reliablity Data
- CAD Symbols, Footprints, and 3D Models
-
Ultra Librarian
-
SamacSys
Software & Part Ecosystem
| Parts | Product Life Cycle | Description | ||
|---|---|---|---|---|
|
Clock Distribution Devices3 |
||||
|
RECOMMENDED FOR NEW DESIGNS |
800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
|||
|
RECOMMENDED FOR NEW DESIGNS |
1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
|||
|
RECOMMENDED FOR NEW DESIGNS |
1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs |
|||
|
Clock Generation Devices6 |
||||
|
NOT RECOMMENDED FOR NEW DESIGNS |
14-Output, Low Jitter Clock generator |
|||
|
RECOMMENDED FOR NEW DESIGNS |
Low Jitter Clock Generator with 14 LVPECL/LVDS/HSTL/29 LVCMOS Outputs |
|||
|
NOT RECOMMENDED FOR NEW DESIGNS |
6 Output, Dual Loop Clock Generator |
|||
|
RECOMMENDED FOR NEW DESIGNS |
1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs |
|||
|
RECOMMENDED FOR NEW DESIGNS |
1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs |
|||
|
RECOMMENDED FOR NEW DESIGNS |
1.2 GHz Clock Distribution IC, Two 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs |
|||
|
Digital Control VGAs2 |
||||
|
Obsolete |
Wide Dynamic Range, High Speed, Digitally Controlled VGA |
|||
|
RECOMMENDED FOR NEW DESIGNS |
Ultralow Distortion IF Dual VGA |
|||
|
Fully Differential Amplifiers1 |
||||
|
RECOMMENDED FOR NEW DESIGNS |
3.3 GHz Ultralow Distortion RF/IF Differential Amplifier |
|||
|
Single-Ended to Differential Amplifiers2 |
||||
|
RECOMMENDED FOR NEW DESIGNS |
Ultralow Distortion Current Feedback Differential ADC Driver |
|||
|
RECOMMENDED FOR NEW DESIGNS |
Ultralow Distortion Differential ADC Driver (Single) |
|||
Can't find the software or driver you need?
Request a Driver/SoftwareEvaluation Kits 3
HSC-ADC-EVALCZ
FPGA-Based Data Capture Kit
Features and Benefits
- 64kB FIFO Depth
- Works with single and multi-channel ADCs
- Use with VisualAnalog® software
- Based on Virtex-4 FPGA
- May require adaptor to interface with some ADC eval boards
- Allows programming of SPI control Up to 644 MSPS SDR / 800MSPS DDR Encode Rates on each channel
- DDR Encode Rates on each channel
Product Detail
Resources
Software
ZIP
29.79 M
ZIP
ZIP
EVAL-AD9634
AD9634 Evaluation Board
Product Detail
This page contains evaluation board documentation and ordering information for evaluating the AD9634.
Resources
EVAL-AD9642
AD9642 Evaluation Board
Product Detail
The AD9642, AD9634, and AD6672 evaluation board, which provides all of the support circuitry required to operate the AD9642, AD9634, and AD6672 in their various modes and configurations. The application software used to interface with the devices is also described.
The AD9642, AD9634, and AD6672 data sheets provide additional information and should be consulted when using the evaluation board. All documents and software tools are available at http://www.analog.com/fifo. For additional information or questions, send an email to highspeed.converters@analog.com.
Resources
Tools & Simulations 4
Virtual Eval - BETA
MathWorks® 1
IBIS Model 1
IBIS Model
Visual Analog
