AD9268
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AD9268

16-Bit, 125 MSPS/105 MSPS/80 MSPS, 1.8 V Dual Analog-to-Digital Converter

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Info: : PRODUCTION tooltip
Info: : PRODUCTION tooltip
Part Models 6
1ku List Price Starting From $133.58
Features
  • SNR = 78.2 dBFS @ 70 MHz and 125 MSPS
  • SFDR = 88 dBc @ 70 MHz and 125 MSPS
  • Low power: 750 mW @ 125 MSPS
  • 1.8 V analog supply operation
  • 1.8 V CMOS or LVDS output supply
  • Integer 1-to-8 input clock divider
  • IF sampling frequencies to 300 MHz
  • −153.6 dBm/Hz small-signal input noise with 200 Ω input impedance @ 70 MHz and 125 MSPS
  • Optional on-chip dither
  • Programmable internal ADC voltage reference
  • See data sheet for additional features
Additional Details
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The AD9268 is a dual, 16-bit, 80 MSPS/105 MSPS/125 MSPS analog-to-digital converter (ADC). The AD9268 is designed to support communications applications where high performance, combined with low cost, small size, and versatility, is desired.

The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth, differential sample-and-hold analog input amplifiers that support a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.

The ADC output data can be routed directly to the two external 16-bit output ports. These outputs can be set to either 1.8 V CMOS or LVDS.

Flexible power-down options allow significant power savings, when desired.

Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface.

The AD9268 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.

PRODUCT HIGHLIGHTS

  1. On-chip dither option for improved SFDR performance with low power analog input.
  2. Proprietary differential input that maintains excellent SNR performance for input frequencies up to 300 MHz.
  3. Operation from a single 1.8 V supply and a separate digital output driver supply accommodating 1.8 V CMOS or LVDS outputs.
  4. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, test modes, and voltage reference mode.
  5. Pin compatibility with the AD9258, allowing a simple migration from 16 bits to 14 bits. The AD9268 is also pin compatible with the AD9251, AD9231, and AD9204 family of products for lower sample rate, low power applications.

APPLICATIONS

  • Communications
  • Diversity radio systems
  • Multimode digital receivers (3G)
    • GSM, EDGE, W-CDMA, LTE,
    • CDMA2000, WiMAX, TD-SCDMA
  • I/Q demodulation systems
  • Smart antenna systems
  • General-purpose software radios
  • Broadband data applications
  • Ultrasound equipment
Part Models 6
1ku List Price Starting From $133.58

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Documentation

Technical Documents 20
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Part Model Pin/Package Drawing Documentation CAD Symbols, Footprints, and 3D Models
AD9268BCPZ-105
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AD9268BCPZ-125
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AD9268BCPZ-80
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AD9268BCPZRL7-105
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AD9268BCPZRL7-125
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AD9268BCPZRL7-80
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Product Lifecycle

PCN

Jun 9, 2021

- 20_0126

Conversion of Select Sizes LFCSP Products from Punched to Sawn and Transfer of Assembly Site to ASE Korea

Filter by Model

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Part Models

Product Lifecycle

PCN

Jun 9, 2021

- 20_0126

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Conversion of Select Sizes LFCSP Products from Punched to Sawn and Transfer of Assembly Site to ASE Korea

Software & Part Ecosystem

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Evaluation Kits 2

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HSC-ADC-EVALCZ

FPGA-Based Data Capture Kit

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HSC-ADC-EVALCZ

FPGA-Based Data Capture Kit

FPGA-Based Data Capture Kit

Features and Benefits

  • 64kB FIFO Depth
  • Works with single and multi-channel ADCs
  • Use with VisualAnalog® software
  • Based on Virtex-4 FPGA
  • May require adaptor to interface with some ADC eval boards
  • Allows programming of SPI control Up to 644 MSPS SDR / 800MSPS DDR Encode Rates on each channel
  • DDR Encode Rates on each channel

Product Detail

The HSC-ADC-EVALCZ high speed converter evaluation platform uses an FPGA based buffer memory board to capture blocks of digital data from the Analog Devices high speed analog-to-digital converter (ADC) evaluation boards. The board is connected to the PC through a USB port and is used with VisualAnalog® to quickly evaluate the performance of high speed ADCs. The evaluation kit is easy to set up. Additional equipment needed includes an Analog Devices high speed ADC evaluation board, a signal source, and a clock source. Once the kit is connected and powered, the evaluation is enabled instantly on the PC.
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EVAL-AD9268

AD9268 Evaluation Board

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EVAL-AD9268

AD9268 Evaluation Board

AD9268 Evaluation Board

Features and Benefits

  • Full featured evaluation board for the AD9650/AD9268/AD9258/AD9251/AD9231/AD9204/AD9269/AD6659
  • SPI interface for setup and control
  • External, on-board oscillator, or AD9517 clocking options
  • Balun/transformer or amplifier input drive options
  • LDO regulator or switching power supply options
  • VisualAnalog® and SPI controller software interfaces

Product Detail

This page contains evaluation board documentation and ordering information for evaluating the AD9268.

The AD9268-125EBZ is an evaluation board for the AD9268, dual 16-bit ADC. This reference design provides all of the support circuitry to operate devices in their various modes and configurations. It is designed to interface directly with the HSC-ADC-EVALCZ data capture card, allowing users to download captured data for analysis. The Visual Analog software package, which is used to interface with the device's hardware, allows users to download captured data for analysis with a user-friendly graphical interface. The SPI controller software package is also compatible with this hardware and allows the user to access the SPI programmable features of the AD9268.

The AD9268 data sheet provides additional information related to device configuration and performance and should be consulted when using these tools. All documents and Visual Analog and SPI Controller are available at the High Speed ADC Evaluation Boards page. For additional information or questions, please email highspeed.converters@analog.com.

Tools & Simulations 5

Reference Designs 1

Schematic of the ADL5535 Driving the AD9268 16-Bit ADC

Low Noise, Low Distortion Single-Ended Input Drive Circuit for Differential Input IF Sampling ADCs

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CN0171

Low Noise, Low Distortion Single-Ended Input Drive Circuit for Differential Input IF Sampling ADCs

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Circuits from the lab

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Low Noise, Low Distortion Single-Ended Input Drive Circuit for Differential Input IF Sampling ADCs

Features and Benefits

  • Single ended to differential conversion
  • 50 ohm impedance matched gain block
  • Matched filter provides noise reduction and antialiasing
View Detailed Reference Design external link

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