AN-1211: Powering the AD9268 Dual Channel 16-Bit, 125 MSPS Analog-to-Digital Converter with the ADP2114 Synchronous Step-Down DC-to-DC Regulator for Increased Efficiency

Circuit Function and Benefits

This circuit utilizes the ADP2114 dual channel synchronous step-down dc-to-dc regulator to provide the individual power supply rails required for the AD9268 dual channel, 16-bit, 125 MSPS, 1.8 V, dual ADC. The ADP2114 is shown to power the AD9268 at 85% efficiency, which is 35% higher efficiency than using a traditional linear regulator solution.

This increased efficiency results in lower system level power consumption with no degradation in the performance of the AD9268. The ADP2114 is a low noise dc-to-dc regulator, which provides two synchronous buck channels (2 A/2 A or 3 A/1 A combinations) at up to 95% efficiency. The ADP2114 has a selectable switching frequency of 300 kHz, 600 kHz, or 1.2 MHz or can be externally synchronized to frequencies from 200 kHz to 2 MHz.

The AD9268 is a low power ADC optimized for communication applications digitizing analog input frequencies up to 300 MHz. This ADC has over 78 dB of SNR, which is ideal for communication applications where high dynamic range and low power are key. The AD9268 includes an on-chip clock divider (1 to 8), which can improve the jitter performance of the incoming clock signal, thereby improving noise performance at higher analog input frequencies. The AD9268’s on-chip dither function can be enabled to improve INL and SFDR.

Circuit Description

Figure 1 shows this ADP2114 power supply solution, which supplies all the necessary input power rails to the AD9268 ADC. The input to the ADP2114 is a +3.6 V dc bus supply with low ripple. The two ADP2114 outputs are connected to the two AD9268 required supplies, including the AVDD rail (+1.8 V at 390 mA) and the DRVDD rail (+1.8 V at 55 mA). The switching frequency of the ADP2114 is set at 1.2 MHz by the 27 kΩ resistor connected to the FREQ pin. The high switching frequency allows the use of smaller external components reducing the overall board space requirement for the power supply solution. The ADP2114 is set for dual 2 A forced PWM output mode by setting the resistor connected to the OPCFG pin to 4.75 kΩ.

Each output utilizes a two-stage LC filter with the first stage utilizing an inductor (L1, L2) and the second stage utilizing a ferrite bead (FB1, FB3) with the feedback loop closed around both stages. This requires a lower loop crossover frequency to maintain stability. An additional ferrite bead (FB2, FB4) is utilized after the regulator for further filtering. After this ferrite bead, the voltages are distributed to the power planes on the PCB where localized decoupling is utilized at the AD9268.

Figure 2 shows an FFT from the AD9268 with a 70 MHz analog input frequency and sample clock of 125 MSPS. The FFT noise floor shows no degradation when compared with a linear regulator power supply solution and shows no measurable frequency components or spurs associated with the switching frequency.

Table 2 shows ac performance data taken on the AD9268 at 125 MSPS using ADP1706 family linear regulators versus the ADP2114 dc-to-dc regulator. Signal-to-noise with respect to full-scale (SNRFS) and spurious free dynamic range (SFDR) are presented across a wide range of analog input frequencies from 10.3 MHz to 200.3 MHz. The results show no degradation in SNR, SFDR, or dynamic range when using the ADP2114 switching regulator design versus a traditional LDO solution.

The efficiency results in Table 3 compare the overall efficiency of an LDO regulator design to the ADP2114 based switching regulator design. Both evaluation boards used for this experiment use the same in-line or bus voltage of 3.6 V in order to calculate the power loss comparison appropriately from input to output for each regulator solution. The switching regulator (ADP2114) design provides an overall improvement in efficiency of 35%. This is roughly a 600 mW power savings for a single AD9268. These savings quickly translate into further power savings when multiple devices are utilized in a system.

Proper layout and circuit partitioning are key to a successful design when using a dc-to-dc regulator such as the ADP2114. Use tightly coupled PCB stackup (power and ground planes) to improve bypassing. Switching inductors should be mounted far from the ADC and sensitive components in the ADC’s clock and signal paths, or on the opposite side of the PCB to help eliminate magnetic flux coupling to sensitive components. Take the time to understand current flow, as well as component or adjacent circuitry placement. Ensure good isolation between circuits.

Common Variations

The AD9258, AD9251, AD9269, AD9231, and AD9204 are footprint-compatible to the AD9268 and can be used as suitable alternatives to the AD9268 if lower resolution or sample rate is required. The ADP2114 has excess current capability for driving a single AD9268. If only one part needs to be powered, the ADP2108 could be considered. In this case a single regulator can be used to power both the AVDD and DRVDD rails if adequate isolation filters are provided between the two supply domains.

Both low dropout (LDO) regulators and switching circuit solutions work when powering ADCs. LDO circuits suffer in efficiency. Switching solutions show increased efficiency and lower power dissipation without degradation to ADC performance. Further efficiency and power savings can be realized when using multiple devices.