AD4082

RECOMMENDED FOR NEW DESIGNS

20-Bit, 10 MSPS, Low Noise, Low Power SAR ADC

Low Noise, Low Power, Fast Precision SAR ADC

Data Sheet (Rev. 0) Product Selection Table

Part Models: 3
1ku List Price: Starting From $25.86

Viewing:

Overview

20-bit resolution, no missing codes
Throughput: 10MSPS, 135ns conversion latency
Noise spectral density: 17.56nV/√Hz,−161.6dBFS/Hz
Low 1/f, low frequency noise (0.1Hz to 10Hz): 174nV rms
Low power: 58.6mW typical at 10MSPS
INL: ±3ppm (typ), ±6ppm (max)
Dynamic range: 94.7dBFS
SNR/THD
- 94.4dB (typ)/−114.5dB (typ) at f_IN = 1kHz
- 93.8dB (typ)/−103dB (typ) at f_IN = 1MHz
Easy Drive
- 6V p-p differential input range
- Continuous signal acquisition
- Linearized, 5μA/MSPS input current
Integrated, low-drift reference buffer and decoupling
Integrated V_CM generation
Digital features and data interface
- Conversion result FIFO, 16K sample depth
- Digital averaging filter with up to 2¹⁰ decimation
SPI configuration
Configurable data interface
- Single lane, DDR, serial LVDS, 200Mbps per lane
- Dual lane, DDR, serial LVDS, 100Mbps per lane
- Single/quad lane SPI data interface
Package
- 49-ball, 5mm × 5mm CSP_BGA, 0.65mm pitch
- Integrated supply decoupling capacitors
Operating temperature range: −40°C to +85°C

The AD4082 is a high speed, low noise, low distortion, 20-bit, Easy Drive, successive approximation register (SAR) analog-to-digital converter (ADC). Maintaining high performance (signal-to-noise and distortion (SINAD) ratio > 92dBFS) at signal frequencies in excess of 1MHz enables the AD4082 to service a wide variety of precision, wide bandwidth data acquisition applications. Simplification of the input anti-alias filter design can be accomplished by applying oversampling along with the integrated digital filtering and decimation to reduce noise and lower the output data rate for applications that do not require the lowest latency of the AD4082.

The AD4082 Easy Drive features reduce both signal chain complexity and power consumption while enabling greater channel density and flexibility in companion component selection. The product input structure was designed to minimize any input dependent signal currents, therefore reducing any converter induced settling artifacts. The continuous acquisition architecture allows settling across the entire conversion cycle, easing ADC driver settling and bandwidth requirements as compared to other high-speed data converters.

The AD4082 includes several elements that simplify data converter integration: a low drift reference buffer, low dropout (LDO) regulators to generate ADC core and digital interface supply rails, and a 16K result data first-in first out (FIFO) that can greatly reduce the load on the digital host. Additionally, critical supply and reference decoupling capacitors are integrated in the package to ensure optimum performance, simplify printed circuit board (PCB) layout, and reduce the overall solution footprint.

APPLICATIONS

Digital imaging
Cell analysis
Spectroscopy
Automated test equipment
High speed data acquisition
Digital control loops, hardware in the loop
Power quality analysis
Source measurement units
Electron and X-ray microscopy
Radar level measurement
Nondestructive test

Part Models: 3
1ku List Price: Starting From $25.86

Documentation

Data Sheet 1

AD4082: 20-Bit, 10 MSPS, Low Noise, Low Power SAR ADC Data Sheet (Rev.0) 05/04/2026

ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.

Part Model	Pin/Package Drawing	Documentation	CAD Symbols, Footprints, and 3D Models
AD4082BBCZ	49-ball CSP_BGA (5 mm x 5 mm x 1.33 mm)	Material Declaration Reliability Report Package Resources	Ultra Librarian SamacSys
AD4082BBCZ-RL	49-ball CSP_BGA (5 mm x 5 mm x 1.33 mm)	Material Declaration Reliability Report Package Resources	Ultra Librarian SamacSys
AD4082BBCZ-RL7	49-ball CSP_BGA (5 mm x 5 mm x 1.33 mm)	Material Declaration Reliability Report Package Resources	Ultra Librarian SamacSys

Software Resources

Can't find the software or driver you need?

Request a Driver/Software

Evaluation Kits

Evaluating the AD4080/AD4081/AD4082 20-Bit, 40/20 MSPS, Differential SAR ADC

Buy Now View Details

Features and Benefits

Full featured evaluation board for the AD4080/AD4081/AD4084
Analysis | Control | Evaluation (ACE) Software plug-in available for device configuration, data capture, and performance evaluation
Flexible analog front end
On-board power solution and precision reference
On-board clock generation circuitry with sampling frequency control via the ACE Software
FMC compatible

Product Details

The EVAL-AD4080-FMCZ is designed to demonstrate the performance of the AD4080, AD4081, AD4082 analog‐to‐digital converter (ADC) and provide access to a limited set of device configuration features through the ACE Software environment. The EVAL-AD4080-FMCZ evaluation kit supports the following AD4080/ AD4081/AD4082 features

Low voltage digital signaling (LVDS) data output interface.
ADC configuration via serial peripheral interface (SPI).
Internal or external generation of 1.1 V regulated supply rails.
Sampling rate capability between 1.25 MSPS and up to 40 MSPS, depending on the specific ADC

The EVAL-AD4080-FMCZ evaluation board was designed for use with the Digilent ZedBoard via the field programmable gate array (FPGA) mezzanine card (FMC) connector. The ZedBoard uses a Xilinx Zynq7000 system on chip (SoC) running Analog Devices, Inc., Kuiper Linux and LIBIIO included on the SD card supplied in the evaluation board kit to facilitate communication with the EVALAD4080-FMCZ, enabling ADC configuration and data capture and to additionally provide the communication link to the host PC and the ACE Software plug-in.

The AD4080 that is physically mounted on the board can be evaluated with any sampling frequency range from 1.25MHz to 40MHz. However, performance of either the AD4081 or AD4082 can also be estimated using this board by setting the sampling frequency to 20MHz or 10MHZ respectively. Note, the captured results for AD4080 running at the reduced sample rate must be used as an estimate of the SNR achievable with the lower speed generics, rather than the actual measurement. Nevertheless, measured SNR for the AD4081 or AD4082 is not lower than that of the AD4080 running in the reduced throughput configuration.