製品概要

機能と利点

  • Flexible reconfigurable radio common platform design
    • 4D2A (4 × 12 GSPS 16-bit DAC + 2 × 6 GSPS 12-bit ADC)
    • 4D1A (4 × 12 GSPS 16-bit DAC + 1 × 6 GSPS 12-bit ADC)
    • Transmit/receive channel bandwidth up to 1.2 GHz/2.4 GHz (4T2R)
    • Transmit/receive channel bandwidth up to 2.4 GHz/2.4 GHz (2T2R)
    • RF DAC/RF ADC output/input −3 dB bandwidth of 5.2 GHz and 7.5 GHz
    • On-chip PLL with multichip synchronization
      • External RF clock input option
  • ADC ac performance at 6 GSPS
    • Full-scale input voltage: 1.475 V p-p
    • Noise density: −153 dBFS/Hz
    • Noise figure: 25.3 dB
    • HD2: −65.2 dBFS at 2.7 GHz
    • HD3: −70.8 dBFS at 2.7 GHz
    • Worst other (excluding HD2 and HD3): −68.5 dBFS at 2.7 GHz
  • DAC ac performance at 12 GSPS
    • Full-scale output current range: 7 mA to 40 mA
    • 2-tone IMD3 (−7 dBFS per tone): −78.9 dBc
    • Noise spectral density (NSD), single-tone at 3.7 GHz: −155.1 dBc/Hz
    • Spurious free dynamic range (SFDR), single-tone at 3.7 GHz: −70 dBc
  • Versatile digital features
    • Selectable interpolation and decimation filters
    • Configurable digital down conversion (DDC) and digital up conversion (DUC)
      • 8 fine complex DUCs and 4 coarse complex DUCs
      • 8 fine complex DDCs and 4 coarse complex DDCs
      • 48-bit numerically controlled oscillator (NCO) per DUC/DDC
      • Option to bypass fine DUC/DDC
    • 15 mm × 15 mm BGA with 0.8 mm pitch
    • Programmable 192 tap programmable filter (PFIR) for receive equalization
      • Supports 4 different profile settings loaded via GPIO
      • Programable delay per data path
      • Receive automatic gain control (AGC) support
        • Fast detect with low latency for fast AGC control
        • Signal monitor for slow AGC control
        • Dedicated AGC support pins
    • Transmit DPD support
      • Fine DUC channel gain control and delay adjust
      • Coarse DDC delay adjust for DPD observation path
    • Versatile digital features
      • Supports real or complex digital data (8-bit, 12-bit, or 16-bit)
      • Configurable digital up/down conversion (DDC/DUC)
        • 8 fine complex DUCs and 4 coarse complex DUCs
        • 8 fine complex DDCs and 4 coarse complex DDCs
        • 2 independent NCO per DUC/DDC
        • Option to bypass fine DUC/DDC
    • Auxiliary features
      • ADC clock driver with selectable divide ratios
      • PA downstream protection circuitry
      • On-chip temperature sensor
      • Programmable GPIO pins
      • ADC clock driver with selectable divide ratios
      • TDD power savings option
    • SERDES JESD204B/C Interface, 16 lanes up to 24.75 Gbps
      • 8 receive lanes for RFDAC
      • 8 transmit lanes for RFADC
      • JESD204B compatible with the maximum 15.5 Gbps lane rate
      • JESD204C compatible with the maximum 24.75 Gbps lane rate
      • Sample/bit repeat mode for receive lane rate matching

製品概要

The transmit signal front-end (TxFE) is a highly integrated device with 16-bit, 12 GSPS maximum sample rate RF digital-to-analog converter (DAC) core and 12-bit, 6 GSPS rate RF analog-to-digital converter (ADC) core. The AD9986 is able to support four transmitter channels and two receiver channels with 4D2A configuration. This device is well suited for 2-antenna and 4-antenna transmitter applications requiring wideband ADCs for the digital predistortion (DPD) observation path. It features a sixteen lane 24.75 Gbps JESD204C or 15.5 Gbps JESD204B data transceiver port, an on-chip clock multiplier, and digital signal processing capability targeted at multiband direct-to-RF radio applications. It supports up to a 6 GSPS complex transmit and receive data rate in single channel mode. The maximum radio band spacing supported in multichannel mode is 1.2 GHz.

APPLICATIONS

  • Wireless communications infrastructure
  • W-CDMA, LTE, LTE-A, massive MIMO
  • Microwave point-to-point, E-band, and 5G mm wave Broadband communications systems
  • Data over cable service interface specification (DOCSIS) 3.0 cable modem termination system (CMTS)
  • Communications test and measurement system

製品ライフサイクル icon-recommended 発売前

新たに発売予定の製品です。技術的な検証が継続中の場合もあります。数量が限られており、設計仕様は量産開始前に変更されることがあります。

評価キット (3)

ソフトウェア & システム

デバイス・ドライバ

API Device Drivers

Device Application Programming Interface (API) C code drivers provided as reference code that allows the user to quickly configure the product using high-level function calls. The library acts as an abstraction layer between the application and the hardware. The API is developed in C99 to ensure agnostic processor and operating system integration. Customers can port this application layer code to their embedded systems by integrating their platform-specific code base to the API HAL layer.

To request this software package, go to the Software Request Form signed in with your MyAnalog account and under “Target Hardware” select “High Speed Data Converters” and choose the desired API product package. You will receive an email notification once the software is provided to you.

ツール

設計ツール

Companion Transport Layer RTL Code Generator Tool (Rev. 1.0)

This command line executable tool generates a Verilog module which implements the JESD204 receive transport layer. The user specifies in a configuration file one or more modes to be supported by the transport layer module. These modes are defined as a set of JESD204 parameter values: L, M, F, S, N', and CF. The transport layer converts JESD204 lane data output from a JESD204 link layer IP to a data bus with a fixed width, containing interleaved virtual converter samples. Both JESD204B and JESD204C link layers are supported.

JESD204x Frame Mapping Table Generator

The JESD204x Frame Mapping Table Generator tool consists of two Windows executables that will allow the user to input any valid combination of JESD204x parameters (L, M, F, S, NP) in order to output a .csv file that illustrates the frame mapping of the JESD204x mode in table format. There is an executable that allows the user to input a single JESD204x mode and another, that allows the user to input the parameters for multiple JESD204x modes in a specified .csv format in order to output a .csv file that illustrates the frame mapping of each of the JESD204x modes that were input into separate tables.

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設計リソース

ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well.  "Zero defects" for shipped products is always our goal.

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価格は1個当たりの米ドルで、米国内における販売価格(FOB)で表示されておりますので、予算のためにのみご使用いただけます。 また、その価格は変更されることがあります。米国以外のお客様への価格は、輸送費、各国の税金、手数料、為替レートにより決定されます。価格・納期等の詳細情報については、弊社正規販売代理店または担当営業にお問い合わせください。なお、 評価用ボードおよび評価用キットの表示価格は1個構成としての価格です。