LTC3618
Info : RECOMMENDED FOR NEW DESIGNS
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LTC3618

Dual 4MHz, ±3A Synchronous Buck Converter for DDR Termination

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Info : RECOMMENDED FOR NEW DESIGNS tooltip
Info : RECOMMENDED FOR NEW DESIGNS tooltip
Part Details
Part Models 10
1ku List Price Starting From $4.90
Features
  • DDR Power Supply, Termination and Reference
  • High Efficiency: Up to 94%
  • Dual Outputs with ±3A Output Current Capability
  • 2.25V to 5.5V Input Voltage Range
  • ±1% Output Voltage Accuracy
  • VTT Output Voltage Down to 0.5V
  • Shutdown Current ≤1μA
  • VTTR = VDDQIN/2, VFB2 = VTTR
  • Adjustable Switching Frequency Up to 4MHz
  • Internal or External Compensation
  • Selectable 0°/90°/180° Phase Shift Between Channels
  • Internal or External Soft-Start for VDDQ, Internal Soft-Start for VTT
  • Power Good Status Outputs
  • Low Profile 4mm × 4mm QFN-24 and TSSOP-24 Packages
  • AEC-Q100 Qualified for Automotive Applications
Additional Details
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The LTC3618 is a dual synchronous step-down regulator using a current mode, constant-frequency architecture. It provides a complete DDR solution with an input voltage range from 2.25V to 5.5V.

The output of the first step-down regulator offers a high accuracy VDDQ supply. A buffered reference generates VTTR at 50% of VDDQIN and drives loads up to ±10mA. The second regulator generates the DDR termination voltage (VTT) equal to VTTR. Both regulators are capable of delivering ±3A of load current at 1MHz switching frequency.

The operating frequency is externally programmable up to 4MHz, allowing the use of small surface mount inductors. 0°, 90°, or 180° of phase shift between the two channels can be selected to minimize input current ripple. For switching noise-sensitive applications, the LTC3618 can be synchronized to an external clock up to 4MHz.

The LTC3618 is offered in leadless 24-pin 4mm × 4mm QFN and thermally enhanced 24-pin TSSOP packages.

APPLICATIONS

  • DDR Memory
  • Supports DDR, DDR2, and DDR3 Standards
  • Tracking Supplies
Part Models 10
1ku List Price Starting From $4.90

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Documentation

Documentation

Part Model Pin/Package Drawing Documentation CAD Symbols, Footprints, and 3D Models
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Product Lifecycle

PCN

Apr 6, 2022

- 22_0068

Laser Top Mark for ETSSOP and TSSOP Packages Assembled in ADPG [PNG] and UTL

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- 22_0068

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Laser Top Mark for ETSSOP and TSSOP Packages Assembled in ADPG [PNG] and UTL

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PRODUCTION

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PRODUCTION

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PRODUCTION

Software & Part Ecosystem

Software & Part Ecosystem

Evaluation Kit

Evaluation Kits 1

reference details image

DC1726A

LTC3618EUF Demo Board | For DDR Termination, 2.25V ≤ VIN ≤ 5.5V, VDDQ = 1.5V/1.8V/2.5V @ ±3A, VTT = 0.5VDDQ @ ±3A, VTTR Current = ±10mA

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DC1726A

LTC3618EUF Demo Board | For DDR Termination, 2.25V ≤ VIN ≤ 5.5V, VDDQ = 1.5V/1.8V/2.5V @ ±3A, VTT = 0.5VDDQ @ ±3A, VTTR Current = ±10mA

LTC3618EUF Demo Board | For DDR Termination, 2.25V ≤ VIN ≤ 5.5V, VDDQ = 1.5V/1.8V/2.5V @ ±3A, VTT = 0.5VDDQ @ ±3A, VTTR Current = ±10mA

Product Detail

Demonstration circuit 1726 is a dual high efficiency monolithic step-down (buck) DC/DC switching regulator designed for double-data-rate (DDR) memory termination in computer systems. The VDDQ output is capable of sourcing and sinking up to 3A with output voltages of 1.5V, 1.8V, 2.5V plus an optional voltage, selected using jumpers. The VTT output can also source and sink up to 3A with an output voltage equal to half of the VDDQ voltage, half of the input voltage or half of an externally applied voltage, selected using a jumper. An additional low current output (VTTR) equal to the VTT voltage capable of sourcing and sinking up to 10mA is included. Input voltage range is from 2.25V to 5.5V with overvoltage protection for transients exceeding 6.5V.

Tools & Simulations

Tools & Simulations 1

LTspice® is a powerful, fast and free simulation software, schematic capture and waveform viewer with enhancements and models for improving the simulation of analog circuits.

To launch ready-to-run LTspice demonstration circuits for this part:

Step 1: Download and install LTspice on your computer.

Step 2: Click on the link in the section below to download a demonstration circuit.

Step 3: If LTspice does not automatically open after clicking the link below, you can instead run the simulation by right clicking on the link and selecting “Save Target As.” After saving the file to your computer, start LTspice and open the demonstration circuit by selecting ‘Open’ from the ‘File’ menu.

Reference Designs

Reference Designs 3

Artix US+ Rail Consolidation – Minimum Rails (AU10P/15P) Power Tree

Minimum Rails for AU10/15P and AU20/25P - Non-Hardware Verified Design

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artix-ultrascale

Minimum Rails for AU10/15P and AU20/25P - Non-Hardware Verified Design

artix-ultrascale

Circuits from the lab

tooltip Info:Circuits from the lab
Minimum Rails for AU10/15P and AU20/25P - Non-Hardware Verified Design

Features and Benefits

  • Xilinx Artix® UltraScale+ devices are the industry’s only cost-optimized FPGAs based on an advanced, production-proven 16nm architecture for best-in-class performance/watt.

  • Analog Devices, Inc. supports power delivery solutions for the Artix Ultrascale+ low-cost designs. Monolithic solutions are used to power Xilinx FPGA and/or SoC rails as well as other system rails. These regulators are highly integrated discrete solutions optimized for cost, efficiency and footprint.

  • ADI provides supporting documentation including power schematics, layout, LTpowerPlanner® and applicable LTpowerPlay® configuration files to enable you to validate the power solution for your application seamlessly.

  • For a complete list power designs and use cases, please contact your local FAE.

  • Key Power for full management devices are used as follows:

    • LTC3307A
    • LTC3309A
    • ADP125
    • LTC3617 (Optional DDR)
    • LTC3618
    • ADM1186 (Optional Monitoring & Sequencing)
View Detailed Reference Design external link
NOVPED iMX6 QP Dev Kit

NXP iMX6 Platform EVK Hardware Verified Design for IO and Robust Power Supply

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nxp-novped-imx6-qp-development-board

NXP iMX6 Platform EVK Hardware Verified Design for IO and Robust Power Supply

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Circuits from the lab

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NXP iMX6 Platform EVK Hardware Verified Design for IO and Robust Power Supply

Features and Benefits

  • Analog Devices has worked closely with FPGA and processor manufacturers to develop verified power solutions that optimize cost, size and efficiency in high performance applications
  • Our reference designs are supported by an intuitive design tool set and IP
  • Our team can provide designs for quick prototypes that can speed time to market in the most complex applications
View Detailed Reference Design external link
Versal HBM Diagram

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xilinx-minimum-rails

xilinx-minimum-rails

Circuits from the lab

tooltip Info:Circuits from the lab

Features and Benefits

  • The Versal HBM series features heterogeneous integration of fast memory, secure connectivity, and adaptive compute to eliminate processing and memory bottlenecks for memory-bound, compute-intensive workloads such as machine learning, database acceleration, next-generation firewalls, and advanced network testers. Analog Devices has worked closely AMD to develop verified power solutions that optimize cost, size and efficiency in high performance applications.
  • ADI provides supporting documentation including LTpowerPlanner and applicable LTpowerPlay configuration files to enable you to validate the power solution for your application seamlessly. For a complete list  power designs and use cases, please contact your local local FAE.
  • ADI has also completed a complete power evaluation report for Mid-High Voltage rails. For a complete report please submit your interest here.

Key power regulators are used for this device as follows:

  • LTC3888-1
  • LTC7051
  • LTC3633A
  • LTC7200S
  • LTC7151S
  • LT8652
  • ADP125
  • LTC3617 (Optional)
  • LTC3618 (Optional)
View Detailed Reference Design external link

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