ADP5014
Info : RECOMMENDED FOR NEW DESIGNS
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ADP5014

Integrated Power Solution with Quad Low Noise Buck Regulators

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Info : RECOMMENDED FOR NEW DESIGNS tooltip
Info : RECOMMENDED FOR NEW DESIGNS tooltip
Part Details
Part Models 1
1ku List Price Starting From $3.52
Features
  • Input voltage range: 2.75 V to 6.0 V
  • Programmable output voltage range: 0.5 V to 0.9 × PVINx
  • Low output noise: ~25 μV rms when VOUT ≤ VREF
  • ±1.0% output accuracy over full temperature range
  • 500 kHz to 2.5 MHz adjustable switching frequency
  • Power regulation
    • Channel 1 and Channel 2: programmable 2 A/4 A sync buck regulators, or single 8 A output in parallel
    • Channel 3 and Channel 4: programmable 1 A/2 A sync buck regulators, or single 4 A output in parallel
  • Flexible parallel operation
  • Precision enable with 0.6 V threshold
  • Manual or sequence mode for power-up and power-down sequence
  • Selective FPWM or PSM operation mode
  • Precision undervoltage comparator
  • Frequency synchronization input or output
  • Active output discharge switch
  • Power-good flag on selective channels via factory fuse
  • UVLO, OVP, OCP, and TSD protection
  • 40-lead, 6 mm × 6 mm LFCSP package
  • −40°C to +125°C junction temperature
Additional Details
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The ADP5014 combines four high performance, low noise buck regulators in a 40-lead LFCSP package. Relying on its low output noise (~25 μV rms when VOUT ≤ VREF), the low noise buck regulator enables the powering up of the noise sensitive signal chain products.

All channels in the ADP5014 integrate high-side and low-side power metal-oxide semiconductor field effect transistors (MOSFET). Channel 1 and Channel 2 deliver a programmable output current of 2 A or 4 A. Combining Channel 1 and Channel 2 in a parallel configuration provides a single output with up to 8 A of current.

Channel 3 and Channel 4 deliver a programmable output current of 1 A or 2 A. Combining Channel 3 and Channel 4 in a parallel configuration can provide a single output with up to 4 A of current.

The ADP5014 features two enable modes. The manual mode has four individual precision enable pins to enable each regulator manually. Alternatively, the sequence mode has one grouped precision enable signal with programmable power-up and power-down delay timers on each rail for specific rail sequence requirements.

The switching frequency of the ADP5014 can be programmed or synchronized to an external clock from 500 kHz to 2.5 MHz.

The ADP5014 offers other key features like selective forced pulse width modulation (FPWM)/power saving mode (PSM), an undervoltage output (UVO), active output discharge, and a power-good flag. Other safety features include input undervoltage lockout (UVLO), overvoltage protection (OVP), overcurrent protection (OCP) and thermal shutdown (TSD).

Applications

  • RF transceiver, high speed analog-to-digital converter (ADC)/digital-to-analog converter (DAC), mixed signal ASIC
  • FPGA and processor applications
  • Security and surveillance
  • Medical applications
Part Models 1
1ku List Price Starting From $3.52

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Documentation

Documentation

Part Model Pin/Package Drawing Documentation CAD Symbols, Footprints, and 3D Models
ADP5014ACPZ-R7
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Software & Part Ecosystem

Software & Part Ecosystem

Evaluation Kit

Evaluation Kits 1

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EVAL-ADP5014

ADP5014 Evaluation Board 

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EVAL-ADP5014

ADP5014 Evaluation Board 

ADP5014 Evaluation Board 

Features and Benefits

  • Full featured evaluation board for the ADP5014
  • Compact solution size
  • 4-layer high glass transition temperature (TG) PCB for superior thermal performance
  • Convenient connections through vertical printed circuit tail pin headers
  • Supply voltage
    • 2.75 V to 6.0 V for PVINx
  • Mode option to select manual or sequence enable
  • Mode option to select PSM or FPWM operation
  • Programmable switching frequency from 500 kHz to 2.5 MHz
  • Frequency synchronization input or output

Product Detail

The ADP5014-EVALZ evaluation board combines four high performance buck regulators in a 40-lead LFCSP package to meet the demanding performance and board space requirements.


Full details on the ADP5014 regulator are provided in the ADP5014 data sheet, available from Analog Devices, Inc. Consult the data sheet in conjunction with user guide UG-1137 when working with this evaluation board.

Tools & Simulations

Tools & Simulations 2

LTspice® is a powerful, fast and free simulation software, schematic capture and waveform viewer with enhancements and models for improving the simulation of analog circuits.

Reference Designs

Reference Designs 1

Artix US+ Rail Consolidation – Minimum Rails (AU10P/15P) Power Tree

Minimum Rails for AU10/15P and AU20/25P - Non-Hardware Verified Design

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artix-ultrascale

Minimum Rails for AU10/15P and AU20/25P - Non-Hardware Verified Design

artix-ultrascale

Circuits from the lab

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Minimum Rails for AU10/15P and AU20/25P - Non-Hardware Verified Design

Features and Benefits

  • Xilinx Artix® UltraScale+ devices are the industry’s only cost-optimized FPGAs based on an advanced, production-proven 16nm architecture for best-in-class performance/watt.

  • Analog Devices, Inc. supports power delivery solutions for the Artix Ultrascale+ low-cost designs. Monolithic solutions are used to power Xilinx FPGA and/or SoC rails as well as other system rails. These regulators are highly integrated discrete solutions optimized for cost, efficiency and footprint.

  • ADI provides supporting documentation including power schematics, layout, LTpowerPlanner® and applicable LTpowerPlay® configuration files to enable you to validate the power solution for your application seamlessly.

  • For a complete list power designs and use cases, please contact your local FAE.

  • Key Power for full management devices are used as follows:

    • LTC3307A
    • LTC3309A
    • ADP125
    • LTC3617 (Optional DDR)
    • LTC3618
    • ADM1186 (Optional Monitoring & Sequencing)
View Detailed Reference Design external link

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