New Content (4)
Features and Benefits
- Flexible, reconfigurable common platform design
- 4 DACs and 4 ADCs (4D4A)
- Supports single, dual, and quad band
- Datapaths and DSP blocks are fully bypassable
- DAC to ADC sample rate ratios of 1, 2, 3, and 4
- On-chip PLL with multichip synchronization
- External RFCLK input option for off-chip PLL
- Maximum DAC sample rate up to 12 GSPS
- Maximum data rate up to 12 GSPS using JESD204C
- Useable analog bandwidth to 8 GHz
- Maximum ADC sample rate up to 4 GSPS
- Maximum data rate up to 4 GSPS using JESD204C
- 7.5 GHz analog input full power bandwidth (−3 dB)
- ADC ac performance at 4 GSPS, input at −2.7 GHz, −1 dBFS
- Full-scale input voltage: 1.4 V p-p
- Noise density: −147.5 dBFS/Hz
- Noise figure: 26.8 dB
- HD2: −67 dBFS
- HD3: −73 dBFS
- Worst other (excluding HD2 and HD3): −79 dBFS at 2.7 GHz
- DAC ac performance at 12 GSPS
- Full-scale output current range: 6.43 mA to 37.75 mA
- Two-tone IMD3 (−7 dBFS per tone): −78.9 dBc
- NSD, single-tone at 3.7 GHz: −155.1 dBc/Hz
- SFDR, single-tone at 3.7 GHz: −70 dBc
- SERDES JESD204B/JESD204C interface, 16 lanes up to 24.75 Gbps
- 8 lanes JESD204B/C transmitter (JTx) and 8 lanes JESD204B/C receiver Rx (JRx)
- JESD204B compliance with the maximum 15.5 Gbps
- JESD204C compliance with the maximum 24.75 Gbps
- Supports real or complex digital data (8-, 12-, 16-, or 24-bit)
- Versatile digital features
- Configurable or by-passable DDCs and DUCs
- 8 fine complex DUCs and 4 coarse complex DUCs
- 8 fine complex DDCs and 4 coarse complex DDCs
- 48-bit NCO per DUC or DDC
- Programmable 192-tap PFIR filter for receive equalization
- Supports 4 different profile settings loaded via GPIO
- Programmable delay per datapath
- Receive AGC support
- Fast detect with low latency for fast AGC control
- Signal monitor for slow AGC control
- Transmit DPD support
- Fine DUC channel gain control and delay adjust
- Coarse DDC delay adjust for DPD observation path
- Auxiliary features
- Fast frequency hopping and direct digital synthesis (DDS)
- Low latency loopback mode (receive datapath data can be routed to the transmit datapaths)
- ADC clock driver with selectable divide ratios
- Power amplifier downstream protection circuitry
- On-chip temperature monitoring unit
- Flexible GPIO pins
- TDD power savings option and sharing ADCs
- 15 mm × 15 mm, 324-ball BGA with 0.8 mm pitch
The AD9081 mixed signal front end (MxFE®) is a highly integrated device with four 16-bit, 12 GSPS maximum sample rate, RF digital-to-analog converter (DAC) cores, and four 12-bit, 4 GSPS rate, RF analog-to-digital converter (ADC) cores. The AD9081 is well suited for applications requiring both wideband ADCs and DACs to process signal(s) that have wide instantaneous bandwidth. The device features eight transmit and eight receive lanes that support 24.75 Gbps/lane JESD204C or 15.5 Gbps/lane JESD204B standards. The device also has an on-chip clock multiplier, and a digital signal processing (DSP) capability targeted at either wideband or multiband direct to RF applications. The DSP datapaths can be bypassed to allow a direct connection between the converter cores and the JESD204 data transceiver port. The device also features low latency loopback and frequency hopping modes targeted at phase array radar system and electronic warfare applications. Two models for the AD9081 are offered. The 4D4AC model supports the full instantaneous channel bandwidth, whereas the 4D4AB model supports a maximum instantaneous bandwidth of 600 MHz per channel by automatically configuring the DSP to limit the instantaneous bandwidth at startup.
- Wireless communications infrastructure
- Microwave point-to-point, E-band and 5G mmWave
- Broadband communications systems
- DOCSIS 3.1 and 4.0 CMTS
- Phased array radar and electronic warfare
- Electronic test and measurement systems
Markets and Technologies
Product Lifecycle Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (4)
The AD9081-FMCA-EBZ evaluation board includes all of the support circuitry required to operate the AD9081 in various modes and configurations. The application software used to interface with the device is also described. The AD9081-FMCA-EBZ evaluation board connects to the Analog Devices, Inc., ADS9-V2EBZ for evaluation with the ACE software. The boards can also interface to commercially available field-programmable gate array (FPGA) development boards from Xilinx® or Intel®. Information on how to use these platforms to evaluate the AD9081 or AD9082 is available in the Using the AD-FMC-SDCARD section.
The ACE software allows the user to set up the AD9081 or AD9082 in various modes, and capture analog-to-digital converter (ADC) data for analysis. The DPGDownloaderLite software generates and transmits vectors to the DACs, which can then be sent to a spectrum analyzer for further analysis. For more details, see the AD9081 and AD9082 data sheets, which must be consulted in conjunction with this user guide when using the evaluation boards.
Features & Benefits
- Fully functional evaluation boards for the AD9081
- PC software for control with ACE software
- On-board clocking provided by the HMC7044 manages device and FPGA clocking
- Option to switch to external direct clocking
- UG-1829: Evaluating the AD9081, AD9082, AD9986, or AD9988 Mixed Signal, Front-End RF Transceiver (Rev. 0)
- Evaluating the AD9082/AD9081 Mixed Signal Front-end (MxFE™) and the AD9988/AD9986 Direct RF Sampling Transceivers
- UG-1578: System Development User Guide for the AD9081 and AD9082 Direct RF Sampling Transceivers (Rev. PrC)
When connected to a specified Analog Devices high speed converter evaluation board, the ADS8-V3EBZ works with ADI evaluation software as a data capture/transmit and control interface. Designed to support high speed data converters with JESD204B/C serial line rates up to 16.375 Gbps, the FPGA on the ADS8-V3EBZ acts as the data receiver for high speed ADC's, and as the transmitter for high speed DAC's.
Limited to use cases where lane rates are less than 16.375 Gbps due to the FPGA capability. (Applies to AD9081 and AD9082.)
Features & Benefits
- Xilinx Kintex UltraScale XCKU040-3FFVA1156E FPGA
- Twenty (20) 16.375 Gbps transceivers supported by one (1) FMC+ connector
- Dual-bank DDR4 SDRAM
- Simple USB 3.0 serial port interface
- One (1) micro SD card is included for high speed converter evaluation board support
When connected to a specified Analog Devices high speed converter evaluation board, the ADS9-V2EBZ works as a data capture/transmit board. Designed to support the highest speed JESD204B/C data converters, the FPGA on the ADS9-V2EBZ acts as the data receiver for high speed ADC's, and as the transmitter for high speed DAC's.
Features & Benefits
Xilinx Kintex Ultrascale+ XCKU15P-2FFVE1517E FPGA.
- One (1) FMC+ connector.
- Twenty (20) 28Gbps transceivers supported by one (1) FMC+ connector.
- HMC DRAM
- Simple USB 3.0 port interface.
- Two micro SD cards are included, "TRX" -- for ADRV9026 evaluation boards and "HSX" -- for MxFE™ evaluation boards.
The Quad-MxFE System Development Platform contains four MxFE® software defined, direct RF sampling transceivers, as well as associated RF front-ends, clocking, and power circuitry. The target application is phased array radars, electronic warfare, and ground-based SATCOM, specifically a 16 transmit/16 receive channel direct sampling phased array at L/S/C band (0.1 GHz to ~5GHz). The Rx & Tx RF front-end has drop-in configurations that allow for customized frequency ranges, depending on the user’s application.
The Quad-MxFE System Development Platform highlights a complete system solution. It is intended as a testbed for demonstrating multi-chip synchronization as well as the implementation of system level calibrations, beamforming algorithms, and other signal processing algorithms. The system is designed to mate with a VCU118 Evaluation Board from Xilinx®, which features the Virtex® UltraScale+™ XCVU9P FPGA, with provided reference software, HDL code, and MATLAB system-level interfacing.
In addition to the Quad-MxFE Digitizing Card, the kit also contains a 16Tx / 16Rx Calibration Board that is used to develop system-level calibration algorithms, or otherwise more easily demonstrate power-up phase determinism in situations pertinent to their own use case. The Calibration Board also allows the user to demonstrate combined-channel dynamic range, spurious, and phase noise improvements and can also be controlled via a free MATLAB add-on when connected to the PMOD interface of the VCU118.
The system can be used to enable quick time-to-market development programs for applications like:
- ADEF (Phased-Array, RADAR, EW, SATCOM)
- Communications Infrastructure (Multiband 5G and mmWave 5G)
- Electronic Test and Measurement
Features & BenefitsQuad-MxFE Digitizing Card
- Multi-Channel, Wideband System Development Platform Using MxFE
- Mates With Xilinx VCU118 Evaluation Board (Not Included)
- 16x RF Receive (Rx) Channels (32x Digital Rx Channels)
- Total 16x 1.5GSPS to 4GSPS ADC
- 48x Digital Down Converters (DDCs), Each Including Complex Numerically-Controlled Oscillators (NCOs)
- 16x Programmable Finite Impulse Response Filters (pFIRs)
- 16x RF Transmit (Tx) Channels (32x Digital Tx Channels)
- Total 16x 3GSPS to 12GSPS DAC
- 48x Digital Up Converters (DUCs) , Each Including Complex Numerically-Controlled Oscillators (NCOs)
- Flexible Rx & Tx RF Front-Ends
- Rx: Filtering, Amplification, Digital Step Attenuation for Gain Control
- Tx: Filtering, Amplification
- On-Board Power Regulation from Single 12V Power Adapter (Included)
- Flexible Clock Distribution
- On-Board Clock Distribution from Single External 500MHz Reference
- Support for External Converter Clock per MxFE
- Mates to Quad-MxFE Digitizing Card & VCU118 PMOD Interface (Cable Included)
- Provides Both Individual Adjacent Channel Loopback and Combined Channel Loopback Options
- Combined Tx Channels Out Via SMA Option
- Combined Rx Channels In Via SMA Option
- On-Board Log Power Detectors With AD5592R Output To VCU118 Over PMOD
- On-Board Power Regulation from Single 12V Power Adapter (Included)
Easy Control Tools and Platform Interfaces to Simplify Software Framework Developments:
- IIO Oscilloscope GUI
- MATLAB Add-Ons & Example Scripts
- Example HDL Builds including JESD204b/JESD204c Bring-Up
- Embedded Software Solutions for Linux and Device Drivers
- MATLAB System Applications GUI
- Multi-Chip Synchronization for Power-Up Phase Determinism
- System-Level Amplitude/Phase Alignment Using NCOs
- Low-Latency ADC-to-DAC Loopback Bypassing JESD Interface
- pFIR Control for Broadband Channel-to-Channel Amplitude/Phase Alignment
- Fast-Frequency Hopping
- Calibration Board MATLAB Driver File
- FPGA Programming MATLAB Script
Software & Systems Requirements
API Device Drivers
Device Application Programming Interface (API) C code drivers provided as reference code that allows the user to quickly configure the product using high-level function calls. The library acts as an abstraction layer between the application and the hardware. The API is developed in C99 to ensure agnostic processor and operating system integration. Customers can port this application layer code to their embedded systems by integrating their platform-specific code base to the API HAL layer.
To request this software package, go to the Software Request Form signed in with your MyAnalog account and under “Target Hardware” select “High Speed Data Converters” and choose the desired API product package. You will receive an email notification once the software is provided to you.
Tools & Simulations
Software and Simulation
Compact Thermal Models
This command line executable tool generates a Verilog module which implements the JESD204 receive transport layer. The user specifies in a configuration file one or more modes to be supported by the transport layer module. These modes are defined as a set of JESD204 parameter values: L, M, F, S, N', and CF. The transport layer converts JESD204 lane data output from a JESD204 link layer IP to a data bus with a fixed width, containing interleaved virtual converter samples. Both JESD204B and JESD204C link layers are supported.
The JESD204x Frame Mapping Table Generator tool consists of two Windows executables that will allow the user to input any valid combination of JESD204x parameters (L, M, F, S, NP) in order to output a .csv file that illustrates the frame mapping of the JESD204x mode in table format. There is an executable that allows the user to input a single JESD204x mode and another, that allows the user to input the parameters for multiple JESD204x modes in a specified .csv format in order to output a .csv file that illustrates the frame mapping of each of the JESD204x modes that were input into separate tables.
AD9081 Companion Parts
Recommended Power Products
- For a low noise linear regulators: ADP1765, ADP7158, ADM7172, ADM7150.
DC-to-DC switching regulators:
Recommended Clock Distribution Device
Recommended Clock Generation Device
Recommended RF Amplifiers
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FPGA Interoperability Reports (1)
Technical Articles (5)
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The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.