AN-722: A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP)


This application note provides design and manufacturing guidance in the use of the lead frame chip scale package (LFCSP). The LFCSP is compliant with JEDEC MO220 and MO229 outlines.


The LFCSP is a near chip scale package (CSP), a plastic encapsulated wire bond package with a copper lead frame substrate in a leadless package format.

Perimeter input/output pads are located on the outside edges of the package. Electrical contact to the printed circuit board (PCB) is made by soldering the perimeter pads and exposed paddle on the bottom surface of the package to the PCB. Heat is efficiently conducted from the package by soldering the exposed thermal paddle (see Figure 1) to the PCB. Stable electrical ground connections are provided through down bonds and through conductive die attach material. Wire bonding is provided using gold wires (see Figure 2). Perimeter and thermal pad finish is plated as Sn/Pb solder or 100% Sn. Packaging is in tape and reel or trays.

Figure 1. Isometric Cut Away View of the LFCSP

Figure 2. Cross Section of the LFCSP

The LFCSP is ideally suited to hand-held mobile application or any application where weight and size is an issue. It allows higher density PCB application than the corresponding leaded package style.

The detailed package outline of the LFCSP is shown in Figure 3.

Figure 3. LFCSP Outline Drawing (JEDEC MO-220)

ADI packages are punched or sawed from a molded strip during final assembly. Half-etching of the lead frame provides mold compound locking features for the perimeter pads and die thermal paddle (see Figure 4). This package is currently characterized as moisture sensitivity (MSL) level 3 (see JEDEC J-STD-20 for MSL levels).

Figure 4. Lead Frame Locking Features

Benefits Over Standard Plastic Packages

LFCSP technology offers a number of significant benefits over standard plastic packages:

  • Reduction in board mounting space as die size is closer to the package size.
  • Superior electrical characteristics are obtained due to elimination of leads reducing electrical path lengths from the die to PCB.
  • Lower thermal resistance because the exposed paddle is soldered to the PCB.
  • The lead frame process utilizes existing proven lead frame package technology.
  • Standard SMT assembly equipment can be used; no underfill is required.
  • High assembly yields can be realized from the selfaligning characteristic of the low mass package during solder attachment.

Board Design Considerations

For optimum performance, special consideration should be given in designing the motherboard and mounting the package. For enhanced thermal, electrical, and board level performance, the exposed paddle on the bottom of the package is soldered to the corresponding thermal land paddle on the PCB. Thermal vias are designed into the PCB land paddle area to further improve heat dissipation.

A number of factors may have a significant effect on mounting the LFCSP package on the board and the quality of solder joints, including board material, board thickness, PCB perimeter pad design, thermal paddle and via design, stencil design, solder paste, and solder profile.

Board Material

Standard epoxy glass substrates (FR-4) are compatible with LFCSP assembly. Use of substrate with lower coefficient of thermal expansion (CTE) can improve reliability. The CTE of a PCB can also be affected by factors such as number of metal layers, laminate materials, trace density, operating environment, site population density, and mounting on the reverse side of the PCB.

Land Pattern Design Guide

The PCB land pattern for the LFCSP is designed based on guidelines developed by the board assembler, or by following an industry standard such as IPC-SM-782. However, because of exposed thermal paddle and the package perimeter pads on the bottom side of the package, constraints should be added to the IPC methodology. The land patterns outlined in ADI application notes are for guideline purposes only, and factor in perimeter pads and package tolerances.

PCB Land Pattern

The PCB land pattern for the LFCSP is defined in Figure 5. The tolerance analysis requires the consideration of:

  • Component tolerances
  • PCB tolerances
  • Accuracy of the equipment used for placing the component

For component tolerances, the profile tolerances usually given in the package outline drawing are converted into maximum material condition (MMC) and least material condition (LMC) based tolerances. The board tolerance defines the difference between the MMC and LMC of each pattern dimension. Here PCB tolerance is assumed to be 0.05 mm; equipment placement tolerance is also assumed to be 0.05 mm.

Figure 5. Land Pattern or PCB Footprint

Figure 6.

Table I. Toe, Heel, and Side Fillets for the LFCSP
JT min Minimum Toe Fillet 0.1 mm
JH min Minimum Heel Fillet 0.05 mm
JS min Minimum Side Fillet 0.0 mm

The minimum values for solder joint fillets, defined in Table I, are used to calculate the land pattern dimensions. The values are selected recognizing that both sides and one end of the leads are embedded in the mold compound, and solder fillets cannot be formed on these sides. The fourth side has the full lead thickness of copper (Cu) exposed on the side of the package. By design, this lead thickness is exposed copper since the leads are cut after plating. The cutting action on the leads is from the bottom to the top of the package, which results in the bottom section of the exposed copper getting covered with solder. It is generally accepted that the toe fillets are formed depending on the type of solder paste used and length of exposure of the package to environmental conditions, but this cannot be guaranteed. IPC/EIA J-STD-001 does not require a toe fillet on the lead edge with exposed copper for bottom-only terminations.

Minimum values of toe, heel, and side fillets are considered for the formation of reliable solder joints. The toe fillet will improve the solder joint reliability, and provision should be made for its formation.

Land Pattern Design Calculations

Find the guideline dimensions for the layout of the land pattern.

Land pattern dimensions are determined initially using the following:

Equation 1

Note: DMIN is the package external outline minimum value.

Table II. XMAX Values Depend on Pitch
Pitch 0.5 mm 0.65 mm 0.8 mm
XMAX mm 0.28 mm 0.37 mm 0.42 mm

As shown in Table II, XMAX is set smaller than bMAX, the max package lead width for 0.5 mm pitch to avoid solder bridging.

Table III. Approximate Values for TT and TS
0.31 mm 0.00 mm

As shown in Table III, TT and TS are the rms values of toe and side tolerances, which account for component, board, and placement tolerances. The calculations for these values are defined in more detail in IPC-SM-782.

The calculation for GDMIN does not account for the leads on adjacent sides of the package. To avoid any solder bridging between the two perpendicular leads on each corner, a minimum clearance, CLL, is needed. This clearance is assumed as ≥ 0.1 mm and the value of GDMIN is determined using the following constraint:

Equation 2


Equation 5

The pad length is determined as follows:

Equation 3

To ensure a robust design and to minimize any possibility of solder bridging during board assembly, a minimum metal-to-metal clearance of 0.2 mm is required. Therefore, a final adjustment to the land pattern is made by overlaying the package outline with the maximum metal dimensions and adjusting the land pattern to maintain 0.2 mm minimum metal-to-metal clearance.

Thermal Paddle Design

The LFCSP is designed with an exposed thermal paddle to conduct heat away from the package and into the PCB. By incorporating thermal vias into the PCB thermal paddle, heat is dissipated more effectively into the inner metal layers of the PCB.

Depending upon the package paddle size, the PCB thermal paddle size is modified to avoid solder bridging between paddle and the perimeter pads. This is done by defining a minimum clearance between the outer edges of the thermal paddle and the inner edges of the perimeter pads as CPL. This minimum clearance is fixed at 0.25 mm to give the maximum size of the thermal paddle as calculated by the following relationship:

Equation 4

The number of thermal vias incorporated into the design will depend on the power dissipation and electrical requirements of the specific application. There is a point of diminishing returns where additional thermal vias may not significantly improve the performance of the package. This is shown in Figure 7 where the effect of number of vias on θJA is plotted for 7 mm × 7 mm, 48-lead packages. A via diameter of 0.3 mm is used for this simulation. As the via pitch decreases, more vias can be incorporated for the same thermal paddle size; however, the incremental performance improvement reduces.

Figure 7. Effect of Number of Thermal Vias on Package Thermal Performance

It is recommended that a via diameter of 0.3 mm to 0.33 mm be used to set a pitch between 1.0 mm and 1.2 mm. A representative of these arrays for a 7 mm × 7 mm 48-lead LFCSP is shown in Figure 8.

Figure 8. PCB Thermal Paddle and Via

In Figure 9, thermal performance θJA is only marginally affected by small multiple voids covering up to 50% of the paddle area for a 6 mm × 6 mm LFCSP. Note: Small voids do not impact the reliability of the solder joints; large voids in the thermal paddle area should be avoided as these can affect electrical and mechanical performance.

Figure 9. Effect of Voids on Thermal Performance

Solder Mask Design

Two types of land pattern are used on the PCB for surface-mount packages: solder mask defined pads (SMD) and non-solder mask defined pads (NSMD).

Because the copper etching process has tighter control than the solder masking process, NSMD is preferred over SMD. The solder mask opening on NSMD pads is larger than the copper pads to allow the solder to adhere to the sides of the copper pad, improving reliability of the solder joints. The difference between these two land patterns is shown in Figure 10.

Figure 10. Cross Sections of NSMD and SMD Pads/Land Patterns

The recommended solder mask opening should be 120 microns to 150 microns larger than the copper pad size to allow for solder mask registration tolerances, typically between 50 microns to 65 microns. The solder mask web must be a minimum of 75 microns in width to adhere to the PCB surface. This constraint allows each land pad to be individually masked for lead pitches of 0.5 mm and higher. However, for 0.4 mm pitch parts with PCB pad width of 0.25 mm, not enough space is available for solder mask web in between the pads. It is recommended to use a trench type solder mask opening where a big opening is designed around all pads on each side of the package with no solder mask in between the pads, as shown in Figure 11. It is better to round the inner edge of the solder mask, especially for corner leads, to allow for enough solder mask web in the corner area.

Figure 11. Solder Mask for (A) Perimeter Lands for 0.5 mm and Higher Pitch Parts, and (B) for 0.4 mm Pitch Parts

Where the thermal land dimension is close to the theoretical maximum, it is recommended that the thermal paddle area should be solder mask defined in order to avoid any solder bridging between the thermal paddle and the perimeter pads. The mask opening should be 100 microns smaller than the thermal land size on all four sides.

Assembly Considerations

Because of the small perimeter pad surface area, care should be taken to form reliable solder joints for the LFCSP. This is further complicated by the large thermal paddle underneath the package and its proximity to the inner edges of the perimeter pads. Although the perimeter pad pattern design suggested earlier might help in eliminating some of the surface-mounting problems, care should be taken in the stencil design and paste printing for both perimeter and thermal pads. Since surface-mount assembly processes vary from company to company, careful process development and characterization is recommended.

Stencil Design for Perimeter Pads

Optimum and reliable solder joints for perimeter pads should have about 50 to 75 μm standoff height and good side fillet on the outside. The first step in achieving good standoff is the solder paste stencil design for perimeter pads. The stencil aperture opening should be designed to achieve maximum paste release. This is accomplished by considering the following two ratios:

Area Ratio = Area of Aperture Opening/Aperture Wall Area Aspect Ratio = Aperture Width/Stencil Thickness For rectangular aperture openings, as required for the LFSCP package, these ratios are given as Area Ratio = LW/2T (L + W) Aspect Ratio = W/T


L and W are the aperture length and width, and T is stencil thickness. For optimum paste release the area and aspect ratios should be greater than 0.66 and 1.5, respectively. It is recommended that the stencil aperture should be 1:1 to PCB pad sizes as both area and aspect ratio targets are easily achieved by this aperture. The stencil should be laser cut and electropolished. Electropolishing helps to smooth the stencil walls and results in better paste release. It is also recommended that the stencil aperture tolerances be tightly controlled, especially for 0.4 mm and 0.5 mm pitch devices, as these tolerances can effectively reduce the aperture size.

Stencil Design for Thermal Paddle

To effectively remove the heat from the package and to enhance electrical performance, the thermal paddle needs to be soldered (bonded) to the PCB thermal paddle, preferably with minimum voids. However, eliminating voids may not be possible because of the presence of thermal vias and the large size of the thermal paddle for larger size packages. Also, out gassing during the reflow process may cause defects (splatter, solder balling) if the solder paste coverage is too big. It is recommended that smaller multiple openings in the stencil should be used instead of one big opening for printing solder paste on the thermal paddle region. This will typically result in 50% to 80% solder paste coverage. Figure 12 shows how to achieve these levels of coverage.

Figure 12. Thermal Paddle Stencil Design for a 7 mm × 7 mm LFCSP Package

Voids within solder joints under the exposed paddle can have an adverse affect on high speed and RF applications as well as on thermal performance. As the LFCSP package incorporates a large center paddle, controlling solder voiding within this region can be difficult. Voids within this ground plane can increase the current path of the circuit. The maximum size for a void should be less than via pitch within the plane. This assures that any one via would not be rendered ineffectual based on any void increasing the current path beyond the distance to the next available via.

Large voids in thermal paddle area should be avoided. To control voids in the thermal paddle area, solder masking may be required for thermal vias to prevent solder wicking inside the via during reflow, thus displacing the solder away from the interface between the package thermal paddle and thermal paddle land on the PCB. There are several methods employed for this purpose, such as via tenting (top or bottom side) using dry film solder mask, via plugging with liquid photo-imagible (LPI) solder mask from the bottom side, or via encroaching. These options are depicted in Figure 13. In case of via tenting, the solder mask diameter should be 100 microns larger than the via diameter.

Figure 13. Solder Mask Options for Thermal Vias (a) via tenting from top; (b) via tenting from bottom; (c) via plugging bottom; and (d) via encroach bottom

A stencil thickness of 0.125 mm is recommended for 0.4 mm and 0.5 mm pitch parts. The stencil thickness can be increased to 0.15 mm to 0.2 mm for coarser pitch parts. A laser-cut, stainless steel stencil is recommended with electropolished trapezoidal walls to improve the paste release. Since not enough space is available underneath the part after reflow, it is recommended that “No Clean” Type 3 paste be used for mounting the LFCSP. Inert atmosphere is also recommended during reflow.

Assembly Process Sequence

Figure 14 shows the typical process flow for mounting surface-mount packages to PCB.

Figure 14. Typical PCB Mounting Process Flow

It is important to include post print and post reflow inspection. The volume of paste printed should be measured either by 2D or 3D techniques. The paste volume should be around 80% to 90% of stencil aperture volume to indicate good paste release. After reflow, the mounted package should be inspected for presence of voids, solder balling, or defects. Cross sectioning may also be required to determine the fillet shape and size and joint standoff height.

Solder Joint Standoff Height and Fillet Formation

The solder joint standoff is a direct function of the amount of paste coverage on the thermal paddle and the type of vias used for LFCSPs with exposed thermal paddle at the bottom. Board mounting studies have shown that the package standoff increases by increasing the paste coverage and by using plugged vias in the thermal paddle region as shown in Table IV.

Table IV. Standoff Height (μm) as a Function of Via Type and Paste Coverage
48 I/O 68 I/O
Paste Coverage 37% 67% 50% 81%
Plugged Via 35 64 67 76
Encroached Via 16 35 32 48

The standoff height varies by the amount of solder that wets or flows into the plate through via (PTH). The encroached via provides an easy path for solder to flow into the PTH and decreases package standoff height, while the plugged via impedes the flow of solder into the vias due to the plugged vias closed barrel end. In addition, the number of vias and their finished hole size will also influence the standoff height for encroached via design. The solder paste type and reactivity can affect standoff height as can PCB thickness, surface finish, and reflow profile.

To achieve 50 micron thick solder joints, which help in improving the board level reliability, it is recommended that the solder paste coverage is at least 50% for plugged vias and 75% for encroached via types.

The peripheral solder joint fillets formation is driven by multiple factors. It should be realized that only the bottom surface of the leads are plated with solder and not the ends. The bare Cu on the side of the leads may oxidize if the packages are stored in an uncontrolled environment. It is possible that a solder fillet will be formed depending on the solder paste (flux) used and the level of oxidation.

The fillet formation is also a function of PCB land size, printed solder volume, and the package standoff height. Since there is only limited solder available, higher standoff controlled by paste coverage on the thermal paddle may not leave enough solder for fillet formation. Conversely, if the standoff is too low, large convex shape fillets may form. Since center paddle coverage and via type have the greatest impact on standoff height, the volume of solder necessary to create optimum fillet varies. Package standoff height and PCB pad sizes will establish the required volume.

Solder Paste Reflow

Reflow profile and peak temperature have a strong influence on void formation.

The reflow temperature should not exceed the maximum temperature for which the package is qualified, according to moisture sensitivity level. The time above liquidus temperature should be around 60 seconds and the ramp rate during preheat should not exceed 3C/sec. Typical Pb-free profile is shown in Figure 15 based on JEDEC J-STD-20C.

Figure 15. Pb-Free Reflow Profile

X-Ray Inspection

Inspection of LFCSP components mounted on PCB is achieved by using transmission of X-ray equipment in the z-plane which can detect bridging, shorts, opens, and solder voids.

Visual Inspection

As the solder joints are located entirely beneath the LFCSP package, visual inspection of the joints from overhead (z-plane) is not possible. An operator uses visual inspection equipment to check for misalignment of the component with the PCB lands, solder bridging, or other process-related failures.


In the event of defects occurring after component attachment, the board assembly will require rework to remove and replace the device. Since most of the soldered joint is inaccessible, correction of the defect will generally require the complete removal and replacement of the component.

Usual applications for LFCSPs involve mounting on small, thin, densely populated PCBs. These factors, coupled with the small size of the components themselves, can lead to challenges in reworking defects. Because of product-dependent complexities, the following is only a guideline and a starting point for the development of a successful rework process for these packages.

The rework process includes the following steps:

  1. Board preparation
  2. Component removal
  3. PCB land clean up
  4. Application of solder paste
  5. Component alignment and placement
  6. Component attachment
  7. Inspection of rework

Board Preparation

Prior to any rework being carried out, it is strongly recommended that the PCB assembly be baked for at least four hours at 125οC in order to remove any residual moisture from the assembly. Components should not exceed the conditions specified on the packaging label.

Component Removal

In order to facilitate the removal of the component from the PCB, the solder joints attaching component to the board should be reflowed. Ideally the reflow profile used for removing the component should be the same as that used for component attachment. However, the time above liquidus can be reduced as long as the reflow is complete. Removed components must not be reused.

Figure 16 shows a typical component removal setup. During reflow, localized heating of the PCB from the bottom side using convective heaters is recommended. Reflow of the solder is achieved by directing hot gas onto the topside of the component. During the reflow of the solder joints, a vacuum cup operating within the confines of the gas shroud attaches to the top side of the component. Once the joints have reflowed, the vacuum lift-off should be automatically engaged during the transition from reflow to cool down. Given the small size of the components, the vacuum pressure should be kept below 0.5 kg/cm2 . This will prevent the component being lifted out before all the joints have been reflowed and avoid pad liftoff.

Figure 16. Solder is Reflowed and the LFCSP is Withdrawn Before Solidification

PCB Land Clean Up

Once the component has been removed, the site should be adequately prepared to receive the replacement device.

Cleaning the site is done in two steps:

  1. Desoldering—Desoldering is achieved through the use of desoldering braid in conjunction with a bladetype soldering iron, as shown in Figure 17. The width of the blade should match the maximum width of the component footprint, and the blade temperature should be low enough to avoid any damage to the circuit board.
  2. Cleaning—The site should be wiped clean using a lintfree cloth and solvent. The solvent is usually specific to the type of paste used in the original assembly.

Figure 17. Desoldering the PCB Lands

Application of Solder Paste

Pad geometries of the LFCSP component present a challenge in producing an even solder line thickness on reflow. A number of critical features of the print stencil should be considered. Stencil alignment accuracy and consistent solder volume transfer is critical for uniform reflow solder processing. The stencil thickness, as well as the etched pattern geometry, determines the precise volume of solder paste deposited. Stencils are usually made of brass or stainless steel, with stainless steel being more durable. As a guide it is recommended to use a 125 microns stencil thickness for LFCSP components.

Stencil apertures should be trapezoidal, as shown in Figure 18, to ensure uniform release of the solder paste and to reduce smearing, thus dimension A is greater than dimension B. The tight geometries and dense population of modern PCBs make accurate and uniform screen-printing of solder paste onto an already populated board very difficult. Thus it is recommended that the solder paste be applied directly onto the base of the component.

Figure 18. Stencil Aperture Geometry

As shown in Figure 19 and Figure 20, the component is:

  1. Placed into a stencil and jig specific to the particular package.
  2. Clamped in place.
  3. Solder is applied using a metal squeegee blade, 125 microns thick stencil with aperture size and shape the same as the package land.

Note: The small standoff height of LFCSPs does not leave much room for cleaning. Therefore, Type 3 (25 to 45 particle size range) no-clean solder paste should be used.

Figure 19. LFCSP is Clamped into Stencil/Jig

Figure 20. Solder Paste is Applied Through Stencil to the Undersurface of the LFCSP

Component Alignment and Placement

The accuracy of component placement of the package is equipment- or process-dependent. LFCSP packages tend to have self-centering ability due to their small mass. Slightly misaligned parts (less than 50% off the pad center) should self-align during reflow as a result of surface tension within the liquid solder. Grossly misaligned packages (greater than 50% off pad center) however, are likely to result in electrical shorts as a result of solder bridges, when they are subjected to reflow.

Having screen-printed the solder paste directly on to the component, the stencil is then unclamped and both the package and stencil are placed onto the pick and place stage of the rework machine, oriented so as to provide the vacuum cup clear access to the top side of the device, as shown in Figure 21. The vacuum cup then lifts the component clear of the stencil without disturbing the solder paste, as shown in Figure 22.

Figure 21. Stencil/Jig is Placed on Rework Machine “Pick and Place” Stage

Figure 22. Vacuum Cup Retrieves LFCSP from Stencil Without Disturbing Solder Paste

Given that the leads on the LFCSP are located on the underside of the package, a split-beam optical system should be used to align the component with the solder pad array on the motherboard (see Figure 23).

Figure 23. Image of LFCSP is Superimposed onto the Image of the Land Pattern to Facilitate Alignment

This type of imaging system will provide an image of the leads that can be superimposed, and by fine adjustment be overlaid onto the mating footprint on the PCB and thus align component with pad array. The alignment should be done at 50× to 100× magnification. The placement machine must have the capability of allowing fine adjustments in x, y, and rotational axes.

Component Attachment

The reflow profile developed during original attachment or removal should be used to attach the new component, since all reflow profile parameters have already been optimized.

Thermal Performance

Material properties are a function of temperature and affect the reliability of the product operation. Thermal management plays an important role in the control of failure mechanisms driven by absolute temperature.

Internal resistance is the resistance at the component level. It is the resistance that exists between the junction or any other circuit element that generates heat and an outside surface of the component. External resistance is the package level resistance. The external thermal resistance is the resistance to the heat flow from the surface of the case to a reference point.

Calculation of θJA for a 7 mm × 7 mm LFCSP

The thermal performance of the package was calculated using ANSYS. The calculations were carried out on a 7 mm × 7 mm, 44 lead-LFCSP with a containing 3.81 mm square die. The model assumed that the package was attached to a 1S2P (1 signal layer, 2 planes) JEDEC thermal test board and constructed using JESD51-5 standard for packages with direct thermal attachment mechanisms, with a metallized area of 76 mm square. The assumed environment was that the package and test board were in a horizontal orientation. θJA was then calculated at power levels between 0.5 W and 2.5 W and at air velocities of 0, 1.0, and 2.5 m/s.

θJA results are depicted graphically in Figure 24. In natural convection, there is a weak dependence of θJA on power. Above an air velocity of 1 m/s, this dependence becomes negligible. The results of the analysis imply most of the heat from the package flows into the board by way of the thermal vias and the fused leads. The metal with high thermal conductivity serves as the main heat dissipation path for the package. At 1 W power, under natural convection conditions, the die temperature is approximately 25οC hotter than the ambient.

Figure 24. Plots of θJA vs. Air Velocity

Modeling Methodology

The thermal performance of the package was calculated using a commercial finite element method software tool (ANSYS). The package lead frame patterns were generated by means of imported AUTOCAD drawings.

The remainder of the package and board features was generated using parametric scripts with ANSYS.

The only geometrical approximation in the model was that the vias in the board are represented as solid cylinders. A derated thermal conductivity was used to represent via material to correct for this modification. These approximations are not expected to affect the accuracy of the model. Because of the symmetry in the package design, a oneeighth model of the package and test board was analyzed.

Electrical Characteristics

Important aspects of electrical design are providing suitable paths for signals and power distribution. Lumped element electrical parameters were computed for an LFCSP. Simulations were performed using the Maxwell Q3D Extractor tool that extracts lumped element partial self and mutual inductance, bulk and mutual capacitance, partial self-resistance and SPICE models. Results were provided at high frequency for all leads and bond wires separately in partial self and mutual inductances. Self-resistances were provided at 100 MHz. The package leads were laid out symmetrically, as shown in Figure 25, so one quarter of the package was modeled to represent the whole package characterization. All conductors were taken to be perfect conductors in the analysis. Most lead frames are at least 150 microns thick and, as the skin depth in copper at 100 MHz is just a few microns, therefore use of perfect conductors is reasonable.

Figure 25. Package Model Top View

The package was mounted on a 15 mil thick FR-4 board. Typical bond wires were defined for each lead using the standard JEDEC4 segment bond wire model. The permittivity of the mold compound was taken as a constant with frequency, and there was no loss term.

Table V. Results for 7 mm × 7 mm × 1.4 mm LQFP
Lead L11 L12 C11 C12
Corner 1.974 0.68 0.3300 0.1027
Center 1.708 0.592 0.2907 0.0823
Ground plane at the same level of seating plane
Lead Count 48
Dimension (l × w × t) 7.0 × 7.0 × 1.4 mm3
Lead Frame
Material EFTEC 64T
Lead Thickness 127 μm
Paddle Size 5 × 5 mm2
Dimension (l × w × t) 4.25 × 4.25 × 0.37 mm3
Wire Material Gold
Gold Conductivity 4.1 × 107 S/m
Wire Diameter 30 μm
Wire Loop Height 203 μm
Length 1.46 mm (Corner)
1.30 mm (Center)

The results from this analysis are tabulated in Table V for 48-lead LQFP 7 mm × 7 mm × 1.4 mm and Table VI for 48-lead LFCSP 7 mm × 7 mm 0.9 mm.


L11: Self Inductance (nH)

L12: Mutual Inductance (nH) to 1st Adjacent Lead

C11: Bulk Capacitance (pF)

C12: Mutual Capacitance (pF) to 1st Adjacent Lead

Table VI. Results for 7 mm × 7 mm × 0.9 mm LFCSP
Lead L11 L12 C11 C12
Corner 1.135 0.211 0.280 0.048
Center 0.909 0.143 0.268 0.043
Ground plane at the same level of seating plane
Lead L11 L12 C11 C12
Corner 1.149 0.213 0.263 0.063
Center 0.920 0.149 0.239 0.056
Ground plane 15 mms below seating plane
Lead Count 48
Dimension (l × w × t) 7.0 × 7.0 × 0.9 mm3
Lead Frame
Material C7025
Lead Thickness 127 μm
Paddle Size 4.75 × 4.75 mms
Dimension (l × w × t) 4.5 × 4.5 × 0.30 mm3
Wire Material Gold
Gold Conductivity 4.1 × 107 S/m
Wire Diameter 30 μm
Wire Loop Height 203 μm
Length 1.35 mm (Corner)
1.18 mm (Center)

The results tabulated in Table VII are for 8-lead LFCSP 3 mm × 2 mm × 0.85 and in Table VIII for 8-lead TSSOP 3 mm × 3 mm × 0.9 mm.

Table VII. Results for 3 mm × 2 mm × 0.85 mm Lead LFCSP
Lead L11 L12 C11 C12
Corner 0.487 0.056 0.168 0.040
Center 0.418 0.039 0.183 0.035
Lead Count 8
Dimension (l × w × t) 3.0 × 2.0 × 0.85 mm3
Lead Frame
Material C-194
Lead Thickness 203.2 μm
Paddle Size 1.94 × 0.65 mm2
Dimension (l × w × t) 1.175 × 0.665 × 0.25 mm3
Wire Material Gold
Gold Conductivity 4.1 × 107 S/m
Wire Diameter 25 μm
Wire Loop Height 203 μm
Length 1.00 mm (Corner)
0.93 mm (Center)
Table VIII. Results for 3 mm × 3 mm × 0.9 mm Lead TSSOP
Lead L11 L12 C11 C12
Maximum 1.486 0.372 0.230 0.058
Minimum 1.275 0.329 0.242 0.052
Lead Count 8
Dimension (l × w × t) 3.0 × 3.0 × 0.9 mm3
Lead Frame
Material C7025
Lead Thickness 127 μm
Paddle Size 2.4 × 1.7 mm2
Dimension (l × w × t) 1.6 × 1.0 × 0.25 mm3
Wire Material Gold
Gold Conductivity 4.1 × 107 S/m
Wire Diameter 25 μm
Wire Loop Height 180 μm
Length 1.23 mm (Corner)
1.03 mm (Center)

Solder Joint Reliability

Reliability is an important aspect in the LFCSP design and its usage for various applications. The I/O pads in the LFCSP are not as compliant as a leaded package and will fail in second level reliability sooner, but are more than adequate for the use conditions outlined in this section. Conditions used for temperature cycling are 15/15/15/15 minutes ramp/dwell.

Reliability Testing

The primary failure mechanism in solder joints is fatigue caused by thermal cycling. This mechanism occurs as a result of repeated exposure to changes in temperature experienced by the solder joints in operation. When solder undergoes an increase in temperature (i.e., change in load), plastic deformation (creep) first occurs. This creep causes an increase in stress within the solder, which increases to plastic yielding (fracture) if the load increases beyond the yield strength of the solder. If the load is maintained at a stable level (or temperature), stress relaxation will occur and all stresses within the solder will completely relax. If the load is then removed and maintained at a stable level, similar stress is imposed on the solder until stress relaxation again occurs. The stress imposed on the solder by the increase and decrease in load causes fatigue damage, which is not repairable and accumulates as the solder is exposed to repeated load cycles.

Reliability of Sn63/Pb37 and Sn95.5/Ag4.0Cu0.5 Solder Joints in 7 mm × 7 mm LFCSP

PCB layout/land sizes were based on the requirements of IPC-SM-782. Devices with SnPb and Pb-free lead finish were assembled in a daisy- chain layout to enable continuous measurement of joint resistance during temperature cycling. Temperature cycling conditions best suited are:

  • Slow ramp rate, i.e., slow change in temperature, to allow the solder to creep
  • Long dwell times to allow stress relaxation

Failures occurred due to open circuit solder joints resulting from fatigue damage. The test conditions for consumer, computer, and telecom applications are shown in Table IX.

Table IX. Typical Use Categories and Conditions as per IPC-SM-785
Application Typical Operating Cycles/Year Typical Service Delta T Max Temp
Consumer +20°C/+55°C 365 1–3 yrs 35°C 55°C
Computer +25°C/+45°C 1460 5 yrs 20°C 45°C
Telecom +10°C/+45°C 365 7–20 yrs 35°C 45°C

Resistance greater than 300 ohms was classified as OPEN. Results were then plotted on a Weibull distribution and typical Weibull characteristics were determined. Using the modified Coffin Manson equation (Norris Landzberg model), comparisons were made with typical use conditions. Results for each solder type, as shown in Table IX, demonstrate the package meets and exceeds the requirements for many use categories in tin/lead and lead-free solder applications.

Table X. Solder Joint Reliability in 7 mm × 7 mm LFCSP
Solder Type Lead Material Cycles to First Fail Typical Life (Years)
Sn63/Pb37 Sn 18756 51
Sn63/Pb37 SnPb 28530 78
Sn95.5/Ag4.0Cu0.5 Sn 16680 46
Sn95.5/Ag4.0Cu0.5 SnPb 27919 76
Sn63/Pb37 Sn 98384 67
Sn63/Pb37 SnPb 149652 103
Sn95.5/Ag4.0Cu0.5 Sn 87494 60
Sn95.5/Ag4.0Cu0.5 SnPb 146450 100
Sn63/Pb37 Sn 21502 59
Sn63/Pb37 SnPb 32706 90
Sn95.5/Ag4.0Cu0.5 Sn 19122 52
Sn95.5/Ag4.0Cu0.5 SnPb 32006 88

Summary of solder joint reliability and Weibull characteristics is shown in Figure 26 and Table XI, respectively.

Figure 26. Weibull Characteristics

Table XI. Summary of Solder Joint Reliability
Parameter Description  Accelerated Test Result
β Slope 9.6031
ρ Correlation Coefficient 0.9828
η Characteristic Life (63.2%) 1697 Cycles
T0.1% Time to 0.1% Cumulative Failure 827 Cycles
T50.0% Time to 50% Cumulative Failure 1634 Cycles


  1. Sample application note for microCSP by Analog Devices (Report AN-617)
  2. Application Notes for Surface Mount Assembly of Amkor’s Microleadframe (MLF) Packages, September 2002
  3. Electrical Report from Amkor Technology: 7.0mm × 7.0mm × 1.4mm, 48 Lead LQFP, 3D Electrical Parasitic Parameters (Report EM-99-19), February 1999
  4. Electrical Report from Amkor Technology: 7.0mm × 7.0mm × 0.9mm 48 Lead MLP2, 3D Electrical Parasitic Parameters (Report EM-99-03), February 1999
  5. Electrical Report from Amkor Technology: 3.0mm × 3.0mm × 0.9mm 8 Lead TSSOP, 3D Electrical Parasitic Parameters (Report EM-98-57), October 1998
  6. Electrical Report from Amkor Technology: 3.0mm × 2.0mm × 0.85mm 8 Lead MLF, 3D Electrical Parasitic Parameters (Report EM-2000-011), July 2000
  7. Reliability Report from Analog Devices: Evaluation of Reliability of SnPb and SnAgCu Solder Joints In 7 × 7mm LFCSP Package, March 2003
  8. Thermal Report from Amkor Technology: 7 mm square body, 44 lead MicroLeadFrame Packages(TM-00-11), April 2000
  9. Lead Frame Chip Scale Package Rework Guidelines, Analog Devices
  10. Websites: electrical/FAQ_3Dsoftware_data.pdf