Features and Benefits
- 300 MHz internal clock rate
- FSK, BPSK, PSK, chirp, AM operation
- Dual integrated 12-bit D/A converters
- Ultrahigh speed comparator, 3 ps rms jitter
- Excellent dynamic performance
- 80 dB SFDR at 100 MHz (±1 MHz) AOUT
- 4× to 20× programmable reference clock multiplier
- Dual 48-bit programmable frequency registers
- Dual 14-bit programmable phase offset registers
- 12-bit programmable amplitude modulation and on/off output shaped keying function
- Single-pin FSK and BPSK data interfaces
- PSK capability via I/O interface
- Linear or nonlinear FM chirp functions with single pin frequency hold function
- Frequency ramped FSK
- <25 ps rms total jitter in clock generator mode
- Automatic bidirectional frequency sweeping
- Sin(x)/x correction
- Simplified control interface
- 10 MHz serial 2-wire or 3-wire SPI-compatible
- 100 MHz parallel 8-bit programming
- 3.3 V single supply
- Multiple power-down functions
- Single-ended or differential input reference clock
- Small, 80-lead LQFP or TQFP with exposed pad
The AD9852 digital synthesizer is a highly integrated device that uses advanced DDS technology, coupled with an internal high speed, high performance D/A converter to form a digitally programmable, agile synthesizer function. When referenced to an accurate clock source, the AD9852 generates a highly stable frequency-, phase-, and amplitude-programmable cosine output that can be used as an agile LO in communications, radar, and many other applications. The innovative high speed DDS core of the AD9852 provides 48-bit frequency resolution (1 μHz tuning resolution with 300 MHz SYSCLK). Retaining 16 bits for phase-to-amplitude conversion ensures excellent spurious-free dynamic range (SFDR).
The circuit architecture of the AD9852 allows the generation of output signals at frequencies up to 150 MHz, which can be digitally tuned at a rate of up to 100 million new frequencies per second. The (externally filtered) cosine wave output can be converted to a square wave by the internal comparator for agile clock generator applications. The device provides two 14-bit phase registers and a single pin for BPSK operation.
For higher-order PSK operation, the I/O interface can be used for phase changes. The 12-bit cosine DAC, coupled with the innovative DDS architecture, provides excellent wideband and narrow-band output SFDR. When configured with the comparator, the 12-bit control DAC facilitates static duty cycle control in the high speed clock generator applications.
The 12-bit digital multiplier permits programmable amplitude modulation, on/off output shaped keying, and precise amplitude control of the cosine DAC output. Chirp functionality is also included for wide bandwidth frequency sweeping applications. The AD9852 programmable 4× to 20× REFCLK multiplier circuit internally generates the 300 MHz system clock from a lower frequency external reference clock. This saves the user the expense and difficulty of implementing a 300 MHz system clock source.
Direct 300 MHz clocking is also accommodated with either single-ended or differential inputs. Single-pin, conventional FSK and the enhanced spectral qualities of ramped FSK are supported. The AD9852 uses advanced 0.35 μ CMOS technology to provide this high level of functionality on a single 3.3 V supply.
The AD9852 is pin-for-pin compatible with the AD9854 single-tone synthesizer. The AD9852 is specified to operate over the extended industrial temperature range of −40°C to +85°C.
- Agile LO frequency synthesis
- Programmable clock generator
- FM chirp source for radar and scanning systems
- Test and measurement equipment
- Commercial and amateur RF exciter
Product Lifecycle Production
At least one model within this product family is in production and available for purchase. The product is appropriate for new designs but newer alternatives may exist.
Evaluation Kits (1)
Documentation & Resources
AN-1389: Recommended Rework Procedure for the Lead Frame Chip Scale Package (LFCSP) (Rev. 0)1/25/2016
AN-769: Generating Multiple Clock Outputs from the AD9540 (Rev. 0)2/14/2015
AN-939: Super-Nyquist Operation of the AD9912 Yields a High RF Output Signal (Rev. 0)2/14/2015
AN-837: DDS-Based Clock Jitter Performance vs. DAC Reconstruction Filter Performance (Rev. 0)2/14/2015
AN-557: An Experimenter's Project: (Rev. 0)2/14/2015
AN-419: A Discrete, Low Phase Noise, 125 MHz Crystal Oscillator for the AD98502/14/2015
AN-237: Choosing DACs for Direct Digital Synthesis2/14/2015
AN-423: Amplitude Modulation of the AD9850 Direct Digital Synthesizer2/14/2015
AN-345: Grounding for Low-and-High-Frequency Circuits2/14/2015
AN-342: Analog Signal-Handling for High Speed and Accuracy2/14/2015
AN-823: Direct Digital Synthesizers in Clocking Applications Time (Rev. 0)2/14/2015
AN-280: Mixed Signal Circuit Technologies2/14/2015
AN-605: Synchronizing Multiple AD9852 DDS-Based Synthesizers (Rev. 0)2/14/2015
AN-927: Determining if a Spur is Related to the DDS/DAC or to Some Other Source (For Example, Switching Supplies) (Rev. 0)2/14/2015
AN-587: Synchronizing Multiple AD9850/AD9851 DDS-Based Synthesizers (Rev. 0)2/14/2015
AN-953: Direct Digital Synthesis (DDS) with a Programmable Modulus (Rev. B)3/27/2008
AN-843: Measuring a Loudspeaker Impedance Profile Using the AD5933 (Rev. A)6/27/2007
AN-851: A WiMax Double Downconversion IF Sampling Receiver Design (Rev. 0)7/26/2006
AN-847: Measuring a Grounded Impedance Profile Using the AD5933 (Rev. A)6/20/2006
AN-772: A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP)2/1/2006
AN-632: Provisionary Data Rates Using the AD9951 DDS as an Agile Reference Clock for the ADN2812 Continuous-Rate CDR (Rev. 0)9/25/2003
AN-543: High Quality, All-Digital RF Frequency Modulation Generation with the ADSP-2181 and the AD9850 DDS9/12/2002
• AN-543 - Monaural FM Transmitter
• AN-543 - Stereo FM Transmitter
Video Portables and Cameras Get HDMI Outputs4/13/2007
Improved DDS Devices Enable Advanced Comm Systems9/1/2006
ADI Buys Korean Mobile TV Chip Maker6/7/2006
The Year of the Waveform Generator12/1/2005
Synchronized Synthesizers Aid Multichannel Systems9/20/2005
DDS IC Initiates Synchronized Signals7/20/2005
Digital Waveform Generator Provides Flexible Frequency Tuning for Sensor Measurement12/7/2004
DDS Simplifies Polar Modulation8/5/2004
Integrated DDS Chip Takes Steps To 2.7 GHz4/28/2004
Speedy A/Ds Demand Stable Clocks3/22/2004
DDS IC Plus Frequency-To-Voltage Converter Make Low-Cost DAC2/5/2004
Simple Circuit Controls Stepper Motors1/8/2004
Two DDS ICs Implement Amplitude-shift Keying12/25/2003
DDS Circuit Generates Precise PWM Waveforms10/2/2003
DDS Device Produces Sawtooth Waveform7/10/2003
400-MSample DDSs Run On Only +1.8 VDC12/1/2002
Digital Potentiometers Vary Amplitude In DDS Devices5/29/2000
Single-Sideband Upconversion of Quadrature DDS Signals to the 800-to-2500-MHz Band5/1/2000 Analog Dialogue
DDS Device Provides Amplitude Modulation9/2/1999
Basics of Designing a Digital Radio Receiver (Radio 101)3/6/1998
Tools & Simulations
AD9852 IBIS Models
ADIsimDDS uses mathematical equations to model and illustrate the overall performance of the selected device. ADIsimDDS calculates the required FTW, given the reference clock frequency and desired output frequency. This tool also models an estimate of the overall spectral performance, and allows the user to explore the effects of external reconstruction filters.
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.View our quality and reliability program and certifications for more information.
|Part Number||Material Declaration||Reliability Data||Pin/Package Drawing||CAD Symbols, Footprints & 3D Models|
|AD9852ASTZ||Material Declaration||Reliability Data||80-Lead LQFP (14mm x 14mm)|
|AD9852ASVZ||Material Declaration||Reliability Data||80-Lead TQFP (14mm x 14mm w/ EP)|
|Wafer Fabrication Data|
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