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ADF4360-9:  集成VCO的时钟发生器PLL

产品详情

ADF4360-9是一款集成电压控制振荡器(VCO)的整数N分频频率合成器,中心频率由外部电感设置,VCO频率范围为65 MHz至400 MHz。

附加的分频器级可以对VCO信号进行分频。CMOS电平输出相当于经过2到31之间的整数值分频的VCO信号。如果需要,此分频信号可以进一步进行二分频处理。

所有片内寄存器均通过简单的三线式接口进行控制。该器件采用3.0 V至3.6 V电源供电,不用时可以关断。

应用

  • 系统时钟产生
  • 测试设备
  • 无线局域网(LAN)
  • 有线电视设备
  • 数据手册,Rev. A,3/08

    特点和优势

    • 主输出频率范围:65 MHz至400 MHz
    • 辅助分频器值为2至31,输出范围为1.1 MHz至200 MHz
    • 3.0 V至3.6 V电源供电
    • 1.8 V逻辑兼容
    • 整数N分频频率合成器
    • 可编程输出功率水平
    • 三线式串行接口
    • 数字锁定检测
    • 软件省电模式

    ADF4360-9功能框图

    文档

    快讯名称 内容类型 文件类型
    ADF4360-9: Clock Generator PLL with Integrated VCO Data Sheet (Rev C, 11/2012) (pdf, 593 kB) 产品数据手册 PDF
    Fundamentals of Frequency Synthesis, Part 1: Phased Locked Loops
    The first of a two-part series on frequency synthesis, with an introduction to Phased Locked Loops. This webcast looks at the need for frequency generation, the techniques from the past present and future, and how to assess the performance of a frequency synthesis, and real world applications. Particular attention will be focused on Phase Locked Loops (PLL's) as frequency synthesizers.
    在线研讨会 WEBCAST
    Fundamentals of Frequency Synthesis, Part 2: Direct Digital Synthesis (DDS)
    This month we conclude our two-part series on frequency synthesis, with an introduction to Direct Digital Synthesis. We will give a basic review of how a direct digital synthesis system works, touching on the inner workings of the DDS engine at a relatively high level. We will also discuss the tradeoffs between PLL and DDS technology as a base choice for frequency synthesis needs.
    在线研讨会 WEBCAST
    UG-476:PLL软件安装指南  (pdf, 0) 用户指导 PDF
    UG-106: ADF4360-9评估板  (pdf, 337 kB)
    集成式PLL和VCO频率合成器
    用户指导 PDF
    RF 手册  (pdf, 988 kB)
    RF IC 选型指南(12/2010)
    概况 PDF
    Why do I see reference spurs? 常见问题解答 HTML
    Why is my phase noise shape changing when I change the PLL settings? 常见问题解答 HTML
    Why doesn't the PLL make my reference input and the clock outputs line up? 常见问题解答 HTML
    How do I optimize my PLL loop for the best phase noise and/or jitter? 常见问题解答 HTML
    My loop is not locking. How do I debug this? 常见问题解答 HTML
    How long does it take for the PLL to lock? 常见问题解答 HTML
    Help! My PLL came unlocked over temperature. 常见问题解答 HTML
    How do I choose between active and passive filter in PLL loop? 常见问题解答 HTML
    Should I reference the passive filter to ground? or supply? 常见问题解答 HTML
    How do the PLLs in the AD951x parts compare to other ADI PLLs? 常见问题解答 HTML
    How does the clock clean-up function of the AD951x parts work? 常见问题解答 HTML
    Why do I want to run a fast PFD frequency? 常见问题解答 HTML
    Is it ok for me to connect the same power supply to both the charge pump and distribution power supply pins? 常见问题解答 HTML
    Why can't I use a bandpass filter for my loop filter? 常见问题解答 HTML
    Should I tie my loop filter to ground or PLL supply? 常见问题解答 HTML
    The loop filter was working great until I changed the divide ratio in PLL. What happened? 常见问题解答 HTML
    How do I use a VCO with a supply greater than 5V? 常见问题解答 HTML
    What suppliers do you recommend for VCO/VCXOs? 常见问题解答 HTML
    Do VCXOs have better phase noise and jitter performance than VCOs? 常见问题解答 HTML
    How do I know which VCO will work best with the AD9510? 常见问题解答 HTML
    Is there an advantage to running a higher VCO frequency than the output frequency? 常见问题解答 HTML
    How do I determine if a VCO is good enough for my purpose? 常见问题解答 HTML
    Is there any difference between the nature of an oscillator's phase noise and the phase noise from a clock chip? 常见问题解答 HTML
    Do different divide ratios cause variations in jitter? 常见问题解答 HTML
    I have a clocking scheme which requires several different division ratios simultaneously. I have a frequency plan, but I'm concerned about crosstalk. How much of a problem is this with your clock distribution chips? 常见问题解答 HTML
    Do divide ratios change the propagation delay? 常见问题解答 HTML
    I want to use the phase offset feature on the AD9510 dividers to generate two signals 90° out of phase. How accurate is the phase offset? 常见问题解答 HTML
    On the AD951x clock ICs, does the phase offset (coarse delay) affect the jitter? 常见问题解答 HTML
    Why doesn't the mini-divider support the divide ratio I want? 常见问题解答 HTML
    I want to use the variable delay adjust, but the jitter is too high. What can I do? 常见问题解答 HTML
    I changed the coarse phase adjust in the evaluation software, but nothing happened. What's going on? 常见问题解答 HTML
    What is the difference between the coarse phase adjust and the fine delay adjust? 常见问题解答 HTML
    What is the fine delay adjust which is available on certain LVDS/CMOS outputs? 常见问题解答 HTML
    Does the fine delay adjust affect the jitter? 常见问题解答 HTML
    Why is the fine delay adjust not available on all the outputs? 常见问题解答 HTML
    Is there a way to cause Input/Output rising edges to be synchronous (zero delay) with the AD9510/11? 常见问题解答 HTML
    Will the AD9510 work without a reference input signal? 常见问题解答 HTML
    What are the best clock sources for a distribution-only design? 常见问题解答 HTML
    I am not using the CLK1 input on the AD9510. Can I just leave it floating? 常见问题解答 HTML
    How good does my input signal need to be? 常见问题解答 HTML
    I turned off my reference but the Digital Lock Detect (DLD) still says I'm locked. 常见问题解答 HTML
    Can I shift the threshold on clocks for single-ended inputs? 常见问题解答 HTML
    The reference input is differential, but my reference is single-ended. Do I need to convert to differential to drive the AD9510? 常见问题解答 HTML
    Will differential or single-ended inputs/outputs improve my jitter? 常见问题解答 HTML
    Why should I use differential rather than single-ended? 常见问题解答 HTML
    How do I feed a single-ended signal into a differential input? 常见问题解答 HTML
    Why do you recommend AC coupling, rather than DC coupling, at the clock inputs? 常见问题解答 HTML
    Are the ADI clock parts stand-alone clock sources or do I still have to buy a clock source to drive these parts? 常见问题解答 HTML
    Which provides better performance - a clock source with sinewave output, or one with differential square wave outputs? 常见问题解答 HTML
    On the AD9510, what is the relationship between clock output jitter and CLK1/CLK2 input slew rate? 常见问题解答 HTML
    I'm trying to write to the part in single-byte mode, but I can't write anything. What am I doing wrong? 常见问题解答 HTML
    Can I use the 951X clocks to drive a mixer (RF LO)? 常见问题解答 HTML
    My applications are RF, not for clocking data converters. Can ADI's 951X ICs be used for RF applications? 常见问题解答 HTML
    I have an input present at the clock input, but I'm not seeing an output? 常见问题解答 HTML
    What happens to the AD9510/11 clock outputs if the Reference Input (REFIN) signal goes away? 常见问题解答 HTML
    What clock frequency comes out of the AD9510 outputs when you first apply power to the device? 常见问题解答 HTML
    Is it possible to impedance match a clock output if it is heavily loaded? (e.g. CL=100pF) 常见问题解答 HTML
    I ran the AD9510 outputs at 1.4 GHz and they seem to work fine. Is there a problem running them at 1.4 GHz? 常见问题解答 HTML
    What should I do with unused channels on the AD9510? 常见问题解答 HTML
    Can I tri-state the AD9510 outputs? 常见问题解答 HTML
    On the AD9510, how can I make sure that the duty cycle of output clocks stays within 40% to 60% duty cycle window? 常见问题解答 HTML
    What is the effect of distributing harmonically related clocks (on chip or on board) in terms of jitter? 常见问题解答 HTML
    Is there any reason to use a transformer on a differential clock output to obtain a "clean" single-ended clock output? 常见问题解答 HTML
    What are some of the advantages/disadvantages of using LVPECL vs. LVDS outputs? 常见问题解答 HTML
    Does the AD9510 support 2.5V PECL? 常见问题解答 HTML
    How much bandwidth is required to process a PECL or LVDS output? 常见问题解答 HTML
    If I use only one of the PECL differential outputs and the unused output is terminated in 50Ω, how will this affect the phase noise or jitter of the single-ended output? 常见问题解答 HTML
    If I change the level of PECL output, does it affect the jitter? 常见问题解答 HTML
    What is the best way to terminate LVPECL outputs to get lowest jitter? 常见问题解答 HTML
    Is it okay to AC-couple PECL or LVDS outputs? 常见问题解答 HTML
    What is the fan-out capability of the CMOS, LVDS, and LVPECL outputs? 常见问题解答 HTML
    What is the proper termination (value and location) for outputs? 常见问题解答 HTML
    Are outputs short-circuit protected? 常见问题解答 HTML
    Are the CMOS drivers on the clock devices complementary? 常见问题解答 HTML
    Some of the schematics in the AD951x data sheets show an LVPECL termination scheme which is different from the classic termination often seen (50 Ω to Vs - 2V, or the Thevenin equivalent thereof). How does this work, and how did you chose 200 Ω for the resistors? Can I use 100 ohms to improve the slew rate (or jitter)? 常见问题解答 HTML
    I have pulled SYNCB low, but I still have output from a channel. Why? 常见问题解答 HTML
    Why can I not get the same output amplitude or rise and fall times as stated in your datasheet? 常见问题解答 HTML
    The AD9510 datasheet says to use an external pull-up resistor on the FUNCTION pin. Why do I need this and what range of resistors will work? 常见问题解答 HTML
    May I use the AD9540 for spread spectrum clocking? 常见问题解答 HTML
    Can I get two clock outputs from the AD9540? 常见问题解答 HTML
    What's the advantage of a DDS-based clock generator? 常见问题解答 HTML
    Why does the AD9540 require special filtering on its analog output. What are the requirements of this filter? 常见问题解答 HTML
    I'm working with optical networks - SONET/SDH. Do ADI's clock chips support these applications? 常见问题解答 HTML
    On my board, I can't get the same low jitter numbers that are shown in the datasheet. Am I doing something wrong? 常见问题解答 HTML
    How do you determine the bandwidth over which phase noise is integrated to obtain jitter? 常见问题解答 HTML
    Using the "ADC SNR method", what is the equivalent bandwidth for the jitter specification? 常见问题解答 HTML
    How do harmonic spurs in the output spectrum affect jitter (random or deterministic)? 常见问题解答 HTML
    When a jitter number is specified without an associated bandwidth, what bandwidth should be assumed? 常见问题解答 HTML
    How do you specify jitter? 常见问题解答 HTML
    How do I use the clock part for jitter clean-up? 常见问题解答 HTML
    If jitter can be calculated from phase noise measurements, is it possible to calculate phase noise from jitter numbers? 常见问题解答 HTML
    Does jitter vary with different clock frequencies? How about phase noise? 常见问题解答 HTML
    I sure can't measure jitter with femtosecond resolution on my scope! How do you do it? How much confidence do you have in the jitter figures that you are quoting for these parts? 常见问题解答 HTML
    Do you guarantee performance shown in ADIsimCLK? 常见问题解答 HTML
    Who do I contact for technical support on ADIsimCLK? 常见问题解答 HTML
    Should I use the minimum charge pump current settings in order to minimize power? 常见问题解答 HTML
    Can I run CMOS outputs at 5V? 常见问题解答 HTML
    Can I use different power supply voltages for the PECL output drivers? 常见问题解答 HTML
    Is .01 uF sufficient for power supply pin bypass? 常见问题解答 HTML
    My application has pretty tight power consumption requirements. I am very interested in the capabilities of the AD9510, but I don't need every feature. Is it possible to turn off the unused features and save power? 常见问题解答 HTML
    Why don't you spec psrr and cmrr in the datasheet? 常见问题解答 HTML
    How do I get two AD951x (with PLL) to synchronize to the same reference input edge? 常见问题解答 HTML
    I really need >10 clock outputs. Can I use multiple chips together and still guarantee that all output clocks are synchronized to REFIN? 常见问题解答 HTML
    How do I synchronize multiple clock devices? 常见问题解答 HTML
    What happens if I run the part in an ambient environment which exceeds 85°C? 常见问题解答 HTML
    How can I determine the die temperature of your device? 常见问题解答 HTML
    My circuit board has both an analog GND and a digital GND. How should I connect the AD9510 pins labeled GND? 常见问题解答 HTML
    What PCB layout recommendations do you have for the of the exposed paddle on the bottom side of the LFCSP package? 常见问题解答 HTML
    What is a PLL Synthesizers and how is it used? 常见问题解答 HTML
    RAQs index 非常见问题解答 HTML
    术语表 专业词汇表 HTML

    设计工具,模型,驱动及软件

    快讯名称 内容类型 文件类型
    ADIsimRF
    ADI公司的ADIsimRF设计工具可以计算RF信号链内的大部分重要参数,包括级联增益、噪声系数、IP3、P1dB和总功耗。
    ADIsim Design/Simulation Tools HTML
    ADIsimPLL™
    ADIsimPLL 可以对ADI公司的最新高性能PLL产品进行快速、可靠的评估。它是目前最全面的PLL频率合成器设计和仿真工具,可实现所有对PLL性能有显著影响的重要非线性效应仿真。ADIsimPLL可以免去设计过程中的至少一项重复劳动,从而加快上市速度。
    ADIsim Design/Simulation Tools HTML
    ADF4360 - Microcontroller No-OS Driver 设备驱动 HTML

    评估套件,原理图符号和PCB封装

    评估板和开发套件查看评估板和套件页面以了解文档和采购信息

    原理图符号和PCB封装— ADI公司提供与当今众多CAD系统兼容的原理图符号和PCB封装(Symbols & Footprints),以便更广泛、更轻松地使用。

    产品推荐及参考设计

    推荐配套产品

    建议配套产品


    推荐ADF4360-9使用的RF混频器
    • 针对10 MHz至6 GHz高动态范围有源混频器,推荐使用ADL5801或双通道ADL5802
    推荐ADF4360-9使用的调制器/解调器 推荐ADF4360-9使用的4分频预分频器
    • 如需低噪声、低功耗、固定RF模块,推荐使用ADF5001
    推荐ADF4360-9使用的PLL有源滤波器
    • 如需超低噪声、轨到轨放大器,推荐使用OP184
    推荐ADF4360-9使用的线性稳压器
    • 针对超低噪声、3V、150mA输出应用,推荐使用ADP150
    • 针对超低噪声、3V、200mA输出应用,推荐使用ADP151
    • 针对高精度5V应用,推荐使用ADP3334
    • 如需升压型3V至5V调节器,推荐使用ADP1613

    推荐电源解决方案

    这些建议有帮助吗?

    Sample样片申请及购买

    价格,封装及供货状态

    ADF4360-9 型号选项
    产品型号 封装 引脚 温度范围 包装和数量 报价*(100-499) 报价*1000 pcs RoHS 查看PCN/PDN 查看库存/
    购买/样片
    ADF4360-9BCPZ 产品状态: 量产 24 ld LFCSP (4x4mm w/2.30mm EP) 24 工业 Tray, 490 $ 3.60 $ 3.06 Y  材料信息 查看PCN 订购 样片
    ADF4360-9BCPZRL 产品状态: 量产 24 ld LFCSP (4x4mm w/2.30mm EP) 24 工业 Reel, 5000 - - Y  材料信息 查看PCN 订购
    ADF4360-9BCPZRL7 产品状态: 量产 24 ld LFCSP (4x4mm w/2.30mm EP) 24 工业 Reel, 1500 - $ 3.06 Y  材料信息 查看PCN 订购
    帮助

    这里所列出的美国报价单仅供预算参考,指美元报价(规定订量的每片美元,美国离岸价),如有修改不再另行通知。由于地区关税、商业税、汇率及手续费原因,国际报价可能不同。对于特殊批量报价,请与您当地的ADI公司办事处或代理商联络。对于评估板和套件的报价是指一个单位价格。

    ADF4360-9 评估板
    产品型号 描述 报价 RoHS 查看PCN/PDN 查看库存/
    购买/样片
    EV-ADF4360-9EB1Z 产品状态: 量产 Evaluation Board $ 121.44 -

    所示报价为单片价格。所列的美国报价单仅供预算参考,指美元报价(每片美国离岸价),如有修改,恕不另行通知。由于地区关税、商业税、汇率及手续费原因,国际报价可能不同。

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