14-Bit, 170 MSPS/250 MSPS, JESD204B, Dual Analog-to-Digital Converter
The AD9250 is a dual, 14-bit ADC with sampling speeds of up to 250 MSPS. The AD9250 is designed to support communications applications where low cost, small size, wide bandwidth, and versatility are desired.
The ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. The ADC cores feature wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. The JESD204B high speed serial interface reduces board routing requirements and lowers pin count requirements for the receiving device.
By default, the ADC output data is routed directly to the two JESD204B serial output lanes. These outputs are at CML voltage levels. Four modes support any combination of M = 1 or 2 (single or dual converters) and L = 1 or 2 (one or two lanes). For dual ADC mode, data can be sent through two lanes at the maximum sampling rate of 250 MSPS. However, if data is sent through one lane, a sampling rate of up to 125 MSPS is supported. Synchronization inputs (SYNCINB± and SYSREF±) are provided.
Flexible power-down options allow significant power savings, when desired. Programmable overrange level detection is supported for each channel via the dedicated fast detect pins.
Programming for setup and control are accomplished using a 3-wire SPI-compatible serial interface.
The AD9250 is available in a 48-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.
- Integrated dual, 14-bit, 170 MSPS/250 MSPS ADC.
- The configurable JESD204B output block supports up to 5 Gbps per lane.
- An on-chip, phase-locked loop (PLL) allows users to provide a single ADC sampling clock; the PLL multiplies the ADC sampling clock to produce the corresponding JESD204B data rate clock.
- Support for an optional RF clock input to ease system board design.
- Proprietary differential input maintains excellent SNR performance for input frequencies of up to 400 MHz.
- Operation from a single 1.8 V power supply.
- Standard serial port interface (SPI) that supports various product features and functions such as controlling the clock DCS, power-down, test modes, voltage reference mode, over range fast detection, and serial output configuration.
- Diversity radio systems
- Multimode digital receivers (3G)
- TD-SCDMA, WiMAX, W-CDMA, CDMA2000, GSM, EDGE, LTE
- DOCSIS 3.0 CMTS upstream receive paths
- HFC digital reverse path receivers
- I/Q demodulation systems
- Smart antenna systems
- Electronic test and measurement equipment
- Radar receivers
- COMSEC radio architectures
- IED detection/jamming systems
- General-purpose software radios
- Broadband data applications
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
The CVT-ADC-FMC-INTPZB interposer board allows certain Analog Devices' High-Speed ADC Evaluation Boards to be used on certain Xilinx® evaluation boards with a FMC connector. The adapter board uses the High Pin Count (HPC) version of the FMC connector, so it can be used on either LPC or HPC hosts (such as the KC705 or VC707). For a list of verified ADI ADC evaluation boards and Xilinx® evaluation boards, please see AD-ADC-FMC Adapter Board (Wiki page where we will have a table of high speed ADC eval boards and comments if needed).
The AD-FMCJESDADC1-EBZ Rapid Prototyping module’s primary purpose is to facilitate understanding/validating/verifying the JESD204B interface within the FPGA development platform ecosystem. This module was designed to comply with all of the FMC physical specifications in terms of mechanical size and mounting hole locations, and as such, PCB layout tradeoffs were made which impact wideband ac performance in the first Nyquist zone. If your objective is AD9250 performance evaluation, please refer to the performance-optimized evaluation boards; their information can be found here.
Virtual Eval - BETA
Virtual Eval is a web application to assist designers in product evaluation of ADCs, DACs, and other ADI products. Using detailed models on Analog’s servers, Virtual Eval simulates crucial part performance characteristics within seconds. Configure operating conditions such as input tones and external jitter, as well as device features like gain or digital down-conversion. Performance characteristics include noise, distortion, and resolution, FFTs, timing diagrams, response plots, and more.
Recommended Clock Drivers
- For low jitter performance , we recommend the AD9510, AD9511, AD9512, AD9513, AD9514, AD9515 or the AD9525 .
- For low jitter performance and integrated VCO , we recommend the AD9516-3 or the AD9516-4 .
- For low jitter performance with jitter cleaning capability , we recommend the AD9523, AD9523-1 or the AD9524 .
Recommended Driver Amplifiers
JESD204 Serial Interface
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FPGA Interoperability Reports
JESD204B Interoperative Report (AD9250 Xilinx Kintex7)
FPGA Interoperability Reports
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Rarely Asked Questions
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ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.
The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.