The AD6672 is an 11-bit intermediate receiver with sampling speeds of up to 250 MSPS. The AD6672 is designed to support communications applications, where low cost, small size, wide bandwidth, and versatility are desired.
The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.
The ADC core output is connected internally to a noise shaping requantizer (NSR) block. The device supports two output modes that are selectable via the serial port interface (SPI). With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6672 supports enhanced SNR performance within a limited region of the Nyquist bandwidth while maintaining an 11-bit output resolution. The NSR block is programmed to provide a bandwidth of up to 33% of the sample clock. For example, with a sample clock rate of 250 MSPS, the AD6672 can achieve up to 73.6 dBFS SNR for an 82 MHz bandwidth at 185 MHz fIN.
With the NSR block disabled, the ADC data is provided directly to the output with an output resolution of 11 bits. The AD6672 can achieve up to 66.6 dBFS SNR for the entire Nyquist bandwidth when operated in this mode.
|Title||Content Type||File Type|
|AD6672: IF Receiver Data Sheet (Rev A, 11/2012) (pdf, 1490 kB)||Data Sheets|
|AN-1142: Techniques for High Speed ADC PCB Layout (pdf, 392 kB)||Application Notes|
|AN-932: Power Supply Sequencing (pdf, 95 kB)||Application Notes|
|AN-878: High Speed ADC SPI Control Software (pdf, 585 kB)||Application Notes|
|AN-282: Fundamentals of Sampled Data Systems (pdf, 2131 kB)||Application Notes|
|AN-737: How ADIsimADC Models an ADC (pdf, 373 kB)||Application Notes|
|AN-807: Multicarrier WCDMA Feasibility (pdf, 969 kB)||Application Notes|
|AN-827: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs (pdf, 203 kB)||Application Notes|
|AN-877: Interfacing to High Speed ADCs via SPI (pdf, 1594 kB)||Application Notes|
|AN-905: VisualAnalog Converter Evaluation Tool Version 1.0 User Manual (pdf, 2124 kB)||Application Notes|
|AN-935: Designing an ADC Transformer-Coupled Front End (pdf, 363 kB)||Application Notes|
|AN-835: Understanding High Speed ADC Testing and Evaluation (pdf, 985 kB)||Application Notes|
|AN-803: Pin Compatible High Speed ADCs Simplify Design Tasks (pdf, 356 kB)||Application Notes|
AN-586: LVDS Outputs for High Speed A/D Converters
(pdf, 207 kB)
High Speed ADCs Uses LVDS (Low-Voltage Differential Signaling) to Minimize Performance Limitations In ADC Applications When Providing High Speed Data Output
AN-812: MicroController-Based Serial Port Interface (SPI) Boot Circuit (pdf, 452,449 bytes)
(pdf, 441 kB)
This application note describes the operation of a general-purpose, microcontroller-based Serial Port Interface (SPI) boot circuit.
|AN-742: Frequency Domain Response of Switched-Capacitor ADCs (pdf, 401 kB)||Application Notes|
|AN-715: A First Approach to IBIS Models: What They Are and How They Are Generated (pdf, 370 kB)||Application Notes|
AN-345: Grounding for Low-and-High-Frequency Circuits
(pdf, 455 kB)
Know Your Ground and Signal Paths for Effective Designs. Current Flow Seeks Path of Least Impedance-Not Just Resistance....
|AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (pdf, 291 kB)||Application Notes|
|AN-741: Little Known Characteristics of Phase Noise (pdf, 1679 kB)||Application Notes|
|The Data Conversion Handbook||Design Handbooks||HTML|
|MT-031: Grounding Data Converters and Solving the Mystery of (pdf, 144 kB)||Tutorials|
|MT-002: What the Nyquist Criterion Means to Your Sampled Data System Design (pdf, 152 kB)||Tutorials|
|MT-001: Taking the Mystery out of the Infamous Formula, "SNR=6.02N + 1.76dB," and Why You Should Care (pdf, 94 kB)||Tutorials|
|MT-075: Differential Drivers for High Speed ADCs Overview (pdf, 183 kB)||Tutorials|
|UG-386: Evaluating the AD9642/AD9634/AD6672 Analog-to-Digital Converters (pdf, 3293 kB)||User Guides|
|AD6672 Quick Start Guide, Revision 2 (pdf, 165 kB)||User Guides|
|MS-2210: Designing Power Supplies for High Speed ADC (pdf, 327 kB)||Technical Articles|
|MS-2124: Understanding AC Behaviors of High Speed ADCs (pdf, 276 kB)||Technical Articles|
Nine Often Overlooked ADC Specifications
(pdf, 445 kB)
Analog-to-digital converters (ADCs) have many specifications; some are more important for a given application than others. Understanding these specifications and controlling external devices affecting the ADC will lead to better performance.
|Analog Devices’ 14-bit A/D Converters Meet Demanding Performance Requirements of Communications, Instrumentation and Test and Measurement Applications (22 Aug 2011)||Press Releases||HTML|
|Glossary of EE Terms||Glossary||HTML|
|Title||Content Type||File Type|
ADIsimADC is Analog Devices' Analog-to-Digital Behavioral Model that accurately models the typical performance characteristics of many of our High Speed Converters. The model faithfully reproduces the errors associated with both static and dynamic features such as AC linearity, clock jitter, and many other product specific anomalies.
|ADIsim Design/Simulation Tools||HTML|
|AD6672 IBIS Model||IBIS Models||HTML|
Recommended Driver Amplifiers for the AD6672
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