ADRV9032R

推荐用于新设计

Integrated 2T2R TDD and FDD RadioVerse Transceiver with Dual Observation Paths

数据手册 (Rev. A) 产品选型表
产品技术资料帮助

ADI公司所提供的资料均视为准确、可靠。但本公司不为用户在应用过程中侵犯任何专利权或第三方权利承担任何责任。技术指标的修改不再另行通知。本公司既没有含蓄的允许，也不允许借用ADI公司的专利或专利权的名义。本文出现的商标和注册商标所有权分别属于相应的公司。
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概述

  • 2 differential transmitters
  • 2 differential receivers
  • 2 differential observation receivers
  • LO tunable range: 450 MHz to 7125 MHz
  • RF range: 350 MHz to 7225 MHz1
  • Maximum transmitter large-signal bandwidth: 200 MHz
  • Maximum transmitter synthesis bandwidth: 450 MHz
  • Maximum receiver signal bandwidth: 200 MHz
  • Maximum observation receiver signal bandwidth: 450 MHz
  • Fully integrated fractional-N RF synthesizer
  • Fully integrated clock synthesizer
  • Dual external LO inputs supporting operation up to 6 GHz
  • JESD204B and JESD204C digital interface: up to 16.5 Gbps
  • TDD and FDD operation
  • Simplifying thermal and power consumption challenges
    • 4.82 W power consumption for the TDD mode, enabled use case with 200 MHz iBW/OBW2

The ADRV9032R is a highly integrated, RF agile transceiver offering two transmitters, two observation receivers for monitoring transmitter channels, two receivers, integrated local oscillator (LO) and clock synthesizers, and digital-signal processing functions to provide a complete transceiver solution. The device provides the high radio performance and low-power consumption demanded by cellular infrastructure applications, software-defined radios, portable instruments, and military communications.

The receiver and transmitter signal paths use a zero-IF (ZIF) architecture that provides wide bandwidth with dynamic range suitable for non-contiguous multicarrier applications. The ZIF architecture has the benefits of low power and RF and bandwidth agility. The lack of aliases and out-of-band images eliminates anti-aliasing and image filters, reducing system size and cost, and making band independent solutions possible.

Please see the Data Sheet for the full description.

APPLICATIONS

  • Software defined radios
  • Portable instrumentation
  • Military communications
  • General-purpose radios
  • Wireless infrastructure
  • TDD and FDD applications
ADRV9032R
Integrated 2T2R TDD and FDD RadioVerse Transceiver with Dual Observation Paths
ADRV9032R Functional Block Diagram ADRV9032R Chip Illustration
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参考资料

数据手册 1

用户手册 1

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软件资源

API Device Drivers 1

Device Application Programming Interface (API) C code drivers provided as reference code allows the user to quickly configure the product using high-level function calls. The library acts as an abstraction layer between the application and the hardware. The API is developed in C99 to ensure agnostic processor and operating system integration. Customers can port this application layer code to their embedded systems/ Baseband Processor by integrating their platform-specific code base to the API HAL layer. To request this software package, go to the Software Request Form signed in with your MyAnalog account and under “Target Technology option - select “Wireless Communications" and choose processor/SOC as "ADRV9032R " , select the check box as well and submit the form. You will receive an email notification with a link for software download.

硬件生态系统

部分模型 产品周期 描述
开关稳压器和控制器 1
LT8625S
推荐用于新设计 具有超低噪声的18V/8A降压型Silent Switcher 3
Modal heading
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评估套件

eval board
schematic 1
schematic 2
schematic 3
ADS10-V1EBZ

ADS10-V1EBZ Evaluation Board

立即购买 更多内容

特性和优点

Xilinx Virtex Ultrascale+ XCVU35P-3FSHV2892E FPGA.

  • One (1) FMC+ connector.
  • Twenty (24) 32.75Gbps transceivers supported by one (1) FMC+ connector.
  • On-board HBM DRAM in FPGA.
  • Simple USB 3.0 port interface.

产品详情

When connected to a specified Analog Devices high speed converter evaluation board, the ADS10-V1EBZ works as a data capture/transmit board. Designed to support the highest speed JESD204B/C data converters, the FPGA on the ADS10-V1EBZ acts as the data receiver for high speed ADC's, and as the transmitter for high speed DAC's.

eval board
schematic 4
schematic 5
schematic 6
EVAL-ADRV903x

ADRV903x 评估系统用户指南

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产品详情

ADRV903x 系列评估系统使客户能够在无需开发定制硬件或软件的情况下评估 ADRV903x 设备。该系统由 ADRV903x 客户评估 (CE) 板和 ADS10-V1EBZ 主板组成，两者均配有相应的壁式适配器电源。  评估软件采用 Analog Devices, Inc. 开发的 分析 | 控制 | 评估 (ACE) 软件，并扩展了 ADRV903x 专用板插件。该插件可与 ACE 在 Windows® 主机 PC 上运行，该主机 PC 通过以太网与 ADS10-V1EBZ 主板通信。ADS10-V1EBZ 用作基带处理器，运行应用程序（ADRV903x 命令服务器），用于控制 ADRV903x 设备并与之通信。

本文档还可作为 ADRV903x 配置器的快速入门指南，该配置器内置于 ACE 的 ADRV903x 板插件中。ADRV903x 配置器允许用户探索 ADRV903x 设备的各种配置，以找到所需的用例配置。ADRV903x 配置器还提供了所选配置的接收器 (Rx)、发射器 (Tx) 和观测接收器 (ORx) 数据路径的频率响应概览。

本用户指南详细介绍了安装 ADRV903x 评估软件、编写现有用例以及评估 ADRV903x 发射器、接收器和观测接收器数据路径所需的步骤。本用户指南的 ADRV903x 配置器部分使用户能够生成新的用例，并查看 ADRV903x 的相应数据路径配置和筛选图。请注意，随着 ADRV903x 配置器开发的进行以及向该工具添加其他功能，本文档也会随之更新。
ADS10-V1EBZ
ADS10-V1EBZ Evaluation Board
ADS10-V1EBZ - Top View ADS10-V1EBZ - Bottom View ADS10-V1EBZ - Angle View
EVAL-ADRV903x
ADRV903x 评估系统用户指南
EVAL-ADRV903x Board Photo Angle View EVAL-ADRV903x Board Photo Top View EVAL-ADRV903x Board Photo Bottom View

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