The AD9648 is a monolithic, dual-channel, 1.8 V supply, 14-bit, 105 MSPS/125 MSPS analog-to-digital converter (ADC). It features a high performance sample-and-hold circuit and on-chip voltage reference. The product uses multistage differential pipeline architecture with output error correction logic to provide 14-bit accuracy at 125 MSPS data rates and to guarantee no missing codes over the full operating temperature range.
The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI).
A differential clock input controls all internal conversion cycles. An optional duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance.
The digital output data is presented in offset binary, Gray code, or twos complement format. A data output clock (DCO) is provided for each ADC channel to ensure proper latch timing with receiving logic. Output logic levels of 1.8 V CMOS or LVDS are supported. Output data can also be multiplexed onto a single output bus.
The AD9648 is available in a 64-lead RoHS compliant LFCSP and is specified over the industrial temperature range (−40°C to +85°C). This product is protected by a U.S. patent.
|Title||Content Type||File Type|
|AD9648: 14-Bit, 125 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter Data Sheet (Rev 0, 08/2011) (pdf, 1119 kB)||Data Sheets|
|AN-1142: Techniques for High Speed ADC PCB Layout (pdf, 392 kB)||Application Notes|
|AN-878: High Speed ADC SPI Control Software (pdf, 585 kB)||Application Notes|
|AN-282: Fundamentals of Sampled Data Systems (pdf, 2131 kB)||Application Notes|
|AN-737: How ADIsimADC Models an ADC (pdf, 373 kB)||Application Notes|
|AN-807: Multicarrier WCDMA Feasibility (pdf, 969 kB)||Application Notes|
AN-808: Multicarrier CDMA2000 Feasibility
(pdf, 1535 kB)
The goal of this application note is to determine the feasibility of implementing a multicarrier CDMA2000 transceiver and what the major subsystem performances must be.
|AN-827: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs (pdf, 203 kB)||Application Notes|
|AN-877: Interfacing to High Speed ADCs via SPI (pdf, 1594 kB)||Application Notes|
|AN-905: VisualAnalog Converter Evaluation Tool Version 1.0 User Manual (pdf, 2124 kB)||Application Notes|
|AN-935: Designing an ADC Transformer-Coupled Front End (pdf, 363 kB)||Application Notes|
|AN-835: Understanding High Speed ADC Testing and Evaluation (pdf, 985 kB)||Application Notes|
|AN-803: Pin Compatible High Speed ADCs Simplify Design Tasks (pdf, 356 kB)||Application Notes|
AN-586: LVDS Outputs for High Speed A/D Converters
(pdf, 207 kB)
High Speed ADCs Uses LVDS (Low-Voltage Differential Signaling) to Minimize Performance Limitations In ADC Applications When Providing High Speed Data Output
AN-812: MicroController-Based Serial Port Interface (SPI) Boot Circuit (pdf, 452,449 bytes)
(pdf, 441 kB)
This application note describes the operation of a general-purpose, microcontroller-based Serial Port Interface (SPI) boot circuit.
|AN-851: A WiMax Double Downconversion IF Sampling Receiver Design (pdf, 262 kB)||Application Notes|
|AN-742: Frequency Domain Response of Switched-Capacitor ADCs (pdf, 401 kB)||Application Notes|
|AN-715: A First Approach to IBIS Models: What They Are and How They Are Generated (pdf, 370 kB)||Application Notes|
AN-345: Grounding for Low-and-High-Frequency Circuits
(pdf, 455 kB)
Know Your Ground and Signal Paths for Effective Designs. Current Flow Seeks Path of Least Impedance-Not Just Resistance....
|AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (pdf, 291 kB)||Application Notes|
|AN-741: Little Known Characteristics of Phase Noise (pdf, 1679 kB)||Application Notes|
|UG-003: Evaluating the AD9650/AD9268/AD9258/AD9251/AD9231/AD9204 Analog-to-Digital Converters (pdf, 2699 kB)||User Guides|
|MS-2210: Designing Power Supplies for High Speed ADC (pdf, 327 kB)||Technical Articles|
|Glossary of EE Terms||Glossary||HTML|
|Title||Content Type||File Type|
ADIsimADC is Analog Devices' Analog-to-Digital Behavioral Model that accurately models the typical performance characteristics of many of our High Speed Converters. The model faithfully reproduces the errors associated with both static and dynamic features such as AC linearity, clock jitter, and many other product specific anomalies.
|ADIsim Design/Simulation Tools||HTML|
|AD9648/AD9628/AD9608 S-Parameters (xls, 746 kB)||S-Parameters||XLS|
|AD9648 IBIS Model||IBIS Models||HTML|
Recommended Driver Amplifiers for the AD9648
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The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.