Dynamically adjust Xilinx FPGA Transceiver power supply 1V±0.25%

2018年05月30日

Analog Devices Guneet Chadha demos how an output voltage of a power supply (1V) to an FPGA core or I/O (eg: high speed Transceiver) can remain within tight tolerances (0.25%) using Power System Management. Also shown, “how to margin” a power supply.

For more information visit analog.com/fpga

Dynamically adjust Xilinx FPGA Transceiver power supply 1V±0.25%

2018年05月30日
Analog Devices Guneet Chadha demos how an output voltage of a power supply (1V) to an FPGA core or I/O (eg: high speed Transceiver) can remain within tight tolerances (0.25%) using Power System Management. Also shown, “how to margin” a power supply.
For more information visit analog.com/fpga
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