CN0276

The signal chain must be designed with care to consider not only amplitude and frequency, but also phase shift and stability. In addition, the resolver rotor winding impedance has both a resistive and an inductive component.

The AD2S1210 RDC excitation signal range is 2 kHz to 20 kHz and can be set in increments of 250 Hz. Most resolvers are specified at a fixed excitation frequency, typically around 10 kHz. Different resolvers have difference phase shifts that must also be considered in the signal chain design.

The excitation signal is applied to the resolver rotor winding which is a non-ideal inductor and has a typical resistive component of 50 Ω to 200 Ω and a reactive component of 0 Ω to 200 Ω. For example, the impedance of the Tamagawa TS2620N21E11 resolver used in the circuit of Figure 1 is 70 Ω + j100 Ω at 10 kHz.

Typical excitation voltages can be as high as 20 V p-p (7.1 V rms), so both maximum current and maximum power consumption of the resolver driver must be considered. The AD8397 was chosen for the circuit because of its wide supply range (24 V), high output current (310 mA peak into 32 Ω on ±12 V supplies), rail-to-rail output voltage, and low thermal resistance package (θ_JA = 47.2°C/W for the 8-pin SOIC EP package).

The excitation output signals from the AD2S1210 are generated from an internal DAC that produces a certain amount of quantization noise and distortion. For this reason, the dual AD8692 op amp is configured as a third-order active Butterworth filter in order to reduce the noise of the drive signals. Similarly, the SIN and COS receiver circuits use two quad AD8694 op amps as an active noise filter.

Signal Chain Design

These factors must be considered in the design of the signal chain:

• AD2S1210 excitation signal output range : 3.2 V min, 3.6 V typical, 4.0 V max
• AD8692 output voltage range: 0.29 V to 4.6 V with +5 V supply
• AD8397 output voltage range: 0.18 V to 5.87 V with +6 V supply.
• AD8397 output voltage range: 0.35 V to 11.7 V with +12 V supply
• Resolver(TS2620N21E11) transformation ratio: 0.5
• Resolver(TS2620N21E11) phase shift: 0°
• AD8694 output voltage range: 0.37 V to 4.6 V with +5 V supply
• AD2S1210 input differential p-p signal range (SIN, COS) is 2.3 V min, 3.15 V typ, 4.0 V max
• Resolver output SIN, COS loads should be equal.
• Resolver output loads should be at least 20 times the resolver output impedance
• Total signal chain phase shift range: n × 180° − 44° ≤ φ ≤ n × 180° + 44°, n is an integer

Resolver Excitation Filter and Driver Circuits

The AD2S1210 excitation signal filter and power amplifier circuit are shown in Figure 2. Careful attention must be paid to the gain and signal levels at each point in the chain so that the AD8397 output driver does not saturate for the maximum excitation (EXE) of 4.0 V p-p from the AD2S1210. Note that because the resolver is driven differentially there are two identical channels as shown in Figure 2 corresponding to the true and complementary EXE outputs, respectively.

The dc gain of the AD8692 filter circuit is −1. For the high performance mode (S1 closed), the gain of the AD8397 driver stage is set for 2.5 (2.49 using actual available resistor values) so that a 4.0 V p-p EXE input produces a 10 V p-p output when using a 12 V supply. This allows 1 V headroom from either rail at the output of the AD8397. For the low power mode (S1 open), the gain is set for 1.28 so that a 4.0 V p-p EXE input produces a 5.12 V p-p output when using a 6 V supply.

The ADG1612 has a typical on-resistance of less than 1 Ω and is ideal for the gain switch. However, because the off capacitance of the switch is typically 72 pF, it should not be connected directly to the input of the op amp. Note that in the circuit it connects R6 to ground, and when off, the capacitance has minimum effect on performance.

The AD8692 is configured as a multiple feedback (MFB) third order Butterworth lowpass filter. It should have a phase shift in range of 180° ± 15°. The design procedure is described in Chapter 8 of Linear Circuit Design Handbook. It is important to select the proper op amp for this filter, and as a general rule, the gain-bandwidth product of the op amp should be at least 20 times the –3dB cutoff frequency of the active filter. In this case, the cutoff frequency is 88 kHz, and the gain-bandwidth product of the AD8692 is 10 MHz, which is 113 times the cutoff frequency. Because the AD8692 is a CMOS op amp, the input bias current is low, and will not significantly affect the dc characteristics of the filter. The input capacitance is 7.5 pF which minimizes the effect on cutoff frequency for the capacitor values chosen in the filter design.

The −3dB cutoff frequency of the filter is 88 kHz, the phase shift is −13° at 10 kHz, and the dc gain is 1 at 10 kHz.

The AD8397 power amplifier can be configured with a gain of 1.28 (low gain mode) and 2.49 (high gain). Phase shift at 10 kHz in the low gain mode is −1.9°, and phase shift in the high gain mode is −5.2°.

The AD8692 third order low pass filter transfer function is shown in Figure 3.

The filter is very effective in reducing the noise on the excitation signals driving the resolver. Figure 4 shows the 10 kHz EXE signal measured directly at the output of the AD2S1210. Figure 5 shows the signal measured at C3 (input to AD8397) and the effectiveness of the filter in removing the noise.

Figures 6 and 7 show the output of the AD8397 measured at one input to the resolver for the low power mode (Figure 6) and the high performance mode (Figure 7). Note that these signals are measured on one side of the resolver input, and the actual differential signal applied to the resolver has twice the amplitude.

Resolver SIN/COS Receiver Circuit and Filter

Figure 8 shows the receiver circuit that includes a third order Butterworth filter and a programmable gain stage. When the driver circuit is in the high performance mode (VCC = 12 V), S1 is open, and the overall gain is 0.35. The input drive to the resolver is 18 V p-p (differential), and the SIN/COS outputs are 9 V p-p differential because the resolver transformation ratio is 0.5. The 9 V p-p differential is 4.5 V p-p single-ended, and when multiplied by the 0.35 gain factor, yields 1.58 V p-p (3.16 V p-p differential) which is the optimum input voltage for the SIN/COS inputs of the AD2S1210. Similarly, in the low power mode S1 is closed, and the overall gain is 0.7 which again provides an optimum input signal level for the SIN/COS inputs of the AD2S1210.

In addition to providing the gain adjustment, the receiver circuit also acts as a third order Butterworth filter with a cutoff frequency of 63 kHz and a phase shift of −18.6° at 10 kHz.

The frequency response of the filter in the low gain and high gain modes is shown in Figures 9 and 10, respectively.

The voltage at the SIN/COS inputs of the AD2S1210 is shown in Figure 11, and is 1.64 V p-p (3.28 V p-p differential).

Figure 12 shows that the total phase shift between the AD2S1210 EXC pin (CH1 yellow) to the SIN input pin (CH2 blue) is ap-proximately 40° which is below the maximum design value of 44°.

Automatic Mode Detection Circuit

The reset circuit shown in Figure 13 uses the ADM6328 micro-processor reset circuit to determine the gain in the driver and receiver based on the value of the VCC voltage. The threshold voltage is set so that if VCC is greater than 11.5 V, the circuit switches to the high performance mode. If VCC is less than 11.5 V, the circuit switches to the low power mode.

Because the ADM6328 consumes only 1 μA it can use the high impedance R1/R3 resistor divider output as its power supply without significant voltage drop.

The ADM6328 has an open drain output, and resistor R2 acts as a pull-up. This ensures that the output swing is independent of the VCC input. The ADM6328 power supply voltage is given by:

The circuit uses the ADM6328-22 that has a typical threshold voltage of 2.2 V, and a maximum of 2.25 V. The maximum VCC threshold voltage is 11.5 V, therefore:

Resistors R1 and R3 are chosen to be 1.6 kΩ and 390 Ω, respectively, giving a ratio of 4.102.

Resolver Driver Power Amplifier Power Dissipation

Because of the relatively low impedance of the resolver and the large VCC voltage, it is important to know the power dissipated in the AD8397 driver amplifier to make sure the maximum power dissipation specification is not exceeded. The maximum power that can be safely dissipated by the AD8397 is limited by the associated rise in junction temperature.

The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150°C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package.

The junction temperature rise can be calculated from the ambient temperature (T_A), the package thermal resistance (θ_JA), and the amplifier power dissipation (P_AMP):

The circuit uses the AD8397ARDZ that is housed in an 8-pin SOIC package with exposed pad (EP), and θ_JA = 47.2°C/W.

The power dissipated in the amplifier, P_AMP, is calculated by subtracting the power dissipated in the load, P_LOAD, from the power supplied by the power supply P_SUPPLY:

The power supplied by the power supplies is calculated by first calculating the average current from the supplies. Note that these calculations neglect the op amp quiescent current and consider only the current due to the excitation current. The equivalent circuit for these calculations is shown in Figure 14.

When using Tamagawa TS2620N21E11 resolver, the impedance is 70 Ω+j100 Ω at 10 kHz. In the high performance state (VCC = 12 V, A = 10 V), the AD8397 power dissipation is 390 mW using the derived equation.

The thermal resistance to ambient, θJA, is 47.2°C/W for the AD8397 (EP package), and therefore the junction temperature rise above ambient is 47.2°C/W × 0.39W = 18.4°.

Power Supplies

The entire circuit operates on either an external VCC of +6 V or +12 V, depending on the mode. The 5 V supply for the circuits is developed using a 5 V, 500 mA ADP7104-5 low dropout regulator (LDO). A 3.3 V ADP7104-3.3 is used to develop the 3.3 V supply. Details of the power circuits can be found in the complete schematic included in the CN0276 Design Support Package (www.analog.com/CN0276-DesignSupport).

PCB Design and Layout Considerations

Even at the lower frequencies associated with the RDC circuits, poor layout can lead to poor performance. For instance, although the resolver operates with a 10 kHz excitation signal, the AD2S1210 operates on an 8.192 MHz clock; therefore it must be treated as a high speed device with respect to layout, grounding, and decoupling. Tutorials MT-031 and MT-101 cover these topics in detail.

A design support package is available for the CN-0276, including complete schematic, PADs and Gerber layout files, and bill of materials. This is located at http://www.analog.com/CN0276-DesignSupport.

System Performance Results

A good method to measure the overall system noise in the circuit is to apply a fixed position to the resolver and generate a histogram of the output codes. This test should be performed with the hysteresis function disabled. The following Figures show the AD2S1210 output histogram of codes for the 10-bit, 12-bit, 14-bit, and 16-bit angular accuracy modes. In each case, the full 16-bits of the RDC are used in generating the histogram, and the circuit is placed in the high performance mode with VCC = +12 V

The histograms show that the AD2S1210 with a low pass filter on the driver and receiver circuit can be achieve high angular resolution in all modes.