The AD9265 is a 16-bit, 125 MSPS analog-to-digital converter (ADC). The AD9265 is designed to support communications applications where high performance combined with low cost, small size, and versatility is desired.
The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic to provide 16-bit accuracy at 125 MSPS data rates and guarantees no missing codes over the full operating temperature range.
The ADC features a wide bandwidth differential sample-and- hold analog input amplifier supporting a variety of user-selectable input ranges. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling single-channel inputs at frequencies well beyond the Nyquist rate. Combined with power and cost savings over previously available ADCs, the AD9265 is suitable for applications in communications, instrumentation and medical imaging.
A differential clock input controls all internal conversion cycles. A duty cycle stabilizer provides the means to compensate for vari- ations in the ADC clock duty cycle, allowing the converters to maintain excellent performance over a wide range of input clock duty cycles. An integrated voltage reference eases design consid- erations.
The ADC output data format is either parallel 1.8 V CMOS or LVDS (DDR). A data output clock is provided to ensure proper latch timing with receiving logic.
Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface. Flexible power-down options allow significant power savings, when desired. An optional on- chip dither function is available to improve SFDR performance with low power analog input signals.
The AD9265 is available in a Pb-free, 48-lead LFCSP and is speci- fied over the industrial temperature range of −40°C to +85°C.Applications
|Title||Content Type||File Type|
|AD9265: 16-Bit, 125 MSPS/105 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter Data Sheet (Rev B, 03/2013) (pdf, 530 kB)||Data Sheets|
|UG-074: Evaluating the AD9265/AD9255 Analog-to-Digital Converters (pdf, 1446 kB)||User Guides|
|MS-2210: Designing Power Supplies for High Speed ADC (pdf, 327 kB)||Technical Articles|
The Differential-signal Advantage for Communications System Design
Understand how differential signal chains and architectures can improve system performance in challenging applications.
(RF Designline, 2/1/2010)
Improve The Design Of Your Passive Wideband ADC Front-End Network
As converter technology improves, so does the demand to resolve very high intermediate frequencies (IFs) accurately at high speeds. This poses two challenges: the converter design itself and the front-end design that couples the signal content to the converter. Even if the converter itself is excellent, the front end must be able to preserve the signal quality too.
(Electronic Design, 3/26/2010)
|Peak High-speed Performance even at low power.||Overview||HTML|
|Analog-to-Digital Converter and Drivers ICs Solutions Bulletin, Volume 10, Issue 2 (pdf, 1358 kB)||Solutions Bulletins|
|Glossary of EE Terms||Glossary||HTML|
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|AD9255/AD9265 S-Parameters (xls, 1329 kB)||S-Parameters||XLS|
|AD9265 IBIS Models||IBIS Models||HTML|
|AD9265 Native FMC Card / ML605 Xilinx Reference Design||FPGA HDL||HTML|
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