AD9467
16-Bit, 200 MSPS/250 MSPS Analog-to-Digital Converter
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- 75.5 dBFS SNR to 210 MHz at 250 MSPS
- 90 dBFS SFDR to 300 MHz at 250 MSPS
- SFDR at 170 MHz at 250 MSPS
- 92 dBFS at −1 dBFS
- 100 dBFS at −2 dBFS
- 60 fs rms jitter
- Excellent linearity at 250 MSPS
- DNL = ±0.5 LSB typical
- INL = ±3.5 LSB typical
- See data sheet for additional features
AD9467-EP supports defense and aerospace applications (AQEC standard)
- Download AD9467-EP data sheet (pdf)
- Extended temperature range (−55°C to +125°C)
- Controlled manufacturing baseline
- Qualification data available on request
- V62/16611 DSCC Drawing Number
The ADC requires 1.8 V and 3.3 V power supplies and a low voltage differential input clock for full performance operation. No external reference or driver components are required for many applications. Data outputs are LVDS compatible (ANSI-644 compatible) and include the means to reduce the overall current needed for short trace distances.
A data clock output (DCO) for capturing data on the output is provided for signaling a new output bit.
The internal power-down feature supported via the SPI typically consumes less than 5 mW when disabled.
Optional features allow users to implement various selectable operating conditions, including input range, data format select, and output data test patterns.
The AD9467 is available in a Pb-free, 72-lead, LFCSP specified over the −40°C to +85°C industrial temperature range.
Product Highlights
- IF optimization capability used to improve SFDR.
- Outstanding SFDR performance for IF sampling applications such as multicarrier, multimode 3G, and 4G cellular base station receivers.
- Ease of use: on-chip reference, high input impedance buffer, adjustable analog input range, and an output clock to simplify data capture.
- Packaged in a Pb-free, 72-lead LFCSP package.
- Clock duty cycle stabilizer (DCS) maintains overall ADC performance over a wide range of input clock pulse widths.
- Standard serial port interface (SPI) supports various product features and functions, such as data formatting (offset binary, twos complement, or Gray coding).
Applications
- Multicarrier, multimode cellular receivers
- Antenna array positioning
- Power amplifier linearization
- Broadband wireless
- Radar
- Infrared imaging
- Communications instrumentation
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AD9467
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ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
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AD9467BCPZ-200 | 72 ld LFCSP (10x10mm, 8.5mm exposed pad) |
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AD9467BCPZ-250 | 72 ld LFCSP (10x10mm, 8.5mm exposed pad) |
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AD9467BCPZRL7-200 | 72 ld LFCSP (10x10mm, 8.5mm exposed pad) |
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AD9467BCPZRL7-250 | 72 ld LFCSP (10x10mm, 8.5mm exposed pad) |
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AD9467SCPZ-250-EP | 72 ld LFCSP (10x10mm, 8.5mm exposed pad) |
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AD9467SCPZ250EPRL7 | 72 ld LFCSP (10x10mm, 8.5mm exposed pad) |
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- AD9467BCPZ-200
- Pin/Package Drawing
- 72 ld LFCSP (10x10mm, 8.5mm exposed pad)
- Documentation
- HTML Material Declaration
- HTML Reliablity Data
- CAD Symbols, Footprints, and 3D Models
- Ultra Librarian
- SamacSys
- AD9467BCPZ-250
- Pin/Package Drawing
- 72 ld LFCSP (10x10mm, 8.5mm exposed pad)
- Documentation
- HTML Material Declaration
- HTML Reliablity Data
- CAD Symbols, Footprints, and 3D Models
- Ultra Librarian
- SamacSys
- AD9467BCPZRL7-200
- Pin/Package Drawing
- 72 ld LFCSP (10x10mm, 8.5mm exposed pad)
- Documentation
- HTML Material Declaration
- HTML Reliablity Data
- CAD Symbols, Footprints, and 3D Models
- Ultra Librarian
- SamacSys
- AD9467BCPZRL7-250
- Pin/Package Drawing
- 72 ld LFCSP (10x10mm, 8.5mm exposed pad)
- Documentation
- HTML Material Declaration
- HTML Reliablity Data
- CAD Symbols, Footprints, and 3D Models
- Ultra Librarian
- SamacSys
- AD9467SCPZ-250-EP
- Pin/Package Drawing
- 72 ld LFCSP (10x10mm, 8.5mm exposed pad)
- Documentation
- HTML Material Declaration
- HTML Reliablity Data
- CAD Symbols, Footprints, and 3D Models
- Ultra Librarian
- SamacSys
- AD9467SCPZ250EPRL7
- Pin/Package Drawing
- 72 ld LFCSP (10x10mm, 8.5mm exposed pad)
- Documentation
- HTML Material Declaration
- HTML Reliablity Data
- CAD Symbols, Footprints, and 3D Models
- Ultra Librarian
- SamacSys
Filter by Model
Part Models
Product Lifecycle
PCN
Jun 26, 2023
- 23_0025
Package Outline Drawing and Data Sheet Revision for Select LFCSP Products in Amkor
AD9467BCPZ-200
PRODUCTION
AD9467BCPZ-250
PRODUCTION
AD9467BCPZRL7-200
PRODUCTION
AD9467BCPZRL7-250
PRODUCTION
AD9467SCPZ-250-EP
PRODUCTION
AD9467SCPZ250EPRL7
PRODUCTION
Filter by Model
Part Models
Product Lifecycle
PCN
Jun 26, 2023
- 23_0025
Package Outline Drawing and Data Sheet Revision for Select LFCSP Products in Amkor
AD9467BCPZ-200
PRODUCTION
AD9467BCPZ-250
PRODUCTION
AD9467BCPZRL7-200
PRODUCTION
AD9467BCPZRL7-250
PRODUCTION
AD9467SCPZ-250-EP
PRODUCTION
AD9467SCPZ250EPRL7
PRODUCTION
Software & Part Ecosystem
FPGA/HDL
Device Drivers
Looking for Evaluation Software? You can find it here
Parts | Product Life Cycle | Description | ||
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Clock Distribution Devices3 |
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RECOMMENDED FOR NEW DESIGNS |
800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
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RECOMMENDED FOR NEW DESIGNS |
1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
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RECOMMENDED FOR NEW DESIGNS |
1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs |
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Clock Generation Devices5 |
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NOT RECOMMENDED FOR NEW DESIGNS |
14-Output, Low Jitter Clock generator |
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NOT RECOMMENDED FOR NEW DESIGNS |
6 Output, Dual Loop Clock Generator |
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RECOMMENDED FOR NEW DESIGNS |
1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs |
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RECOMMENDED FOR NEW DESIGNS |
1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs |
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RECOMMENDED FOR NEW DESIGNS |
1.2 GHz Clock Distribution IC, Two 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs |
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Digital Control VGAs3 |
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Obsolete |
Wide Dynamic Range, High Speed, Digitally Controlled VGA |
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Obsolete |
Wide Dynamic Range, High Speed, Digitally Controlled VGA |
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LAST TIME BUY |
100 MHz TO 4000 MHz RF/IF Digitally Controlled VGA |
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Fully Differential Amplifiers1 |
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RECOMMENDED FOR NEW DESIGNS |
3.3 GHz Ultralow Distortion RF/IF Differential Amplifier |
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Single-Ended to Differential Amplifiers1 |
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RECOMMENDED FOR NEW DESIGNS |
Ultralow Distortion Current Feedback Differential ADC Driver |
Can't find the software or driver you need?
Request a Driver/SoftwareEvaluation Kits 1
EVAL-AD9467
AD9467 Evaluation Board
Product Detail
This page contains evaluation board documentation and ordering information for evaluating the AD9467.
Resources
Evaluation Kits1
Tools & Simulations 5
Virtual Eval - BETA
IBIS Model 1
Visual Analog
ADIsimRF
MathWorks® 1
Reference Designs 1
CN0227
High Performance, 16-Bit, 250 MSPS Wideband Receiver with Antialiasing Filter