AD9265
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AD9265

16-Bit, 125 MSPS/105 MSPS/80 MSPS, 1.8 V Analog-to-Digital Converter

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Part Details
Part Models 6
1ku List Price Starting From $63.92
Features
  • SNR = 79.0 dBFS @ 70 MHz and 125 MSPS
  • SFDR = 93 dBc @ 70 MHz and 125 MSPS
  • Low power: 373 mW @ 125 MSPS
  • 1.8 V analog supply operation
  • 1.8 V CMOS or LVDS output supply
  • Integer 1-to-8 input clock divider
  • IF sampling frequencies to 300 MHz
  • −154.3 dBm/Hz small signal input noise with 200 Ω input impedance @ 70 MHz and 125 MSPS
  • Optional on-chip dither
  • Programmable internal ADC voltage reference
  • Integrated ADC sample-and-hold inputs
  • Flexible analog input range: 1 V p-p to 2 V p-p
  • Differential analog inputs with 650 MHz bandwidth ADC clock duty cycle stabilizer
  • Serial port control
  • User-configurable, built-in self-test (BIST) capability Energy-saving power-down modes

Additional Details
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The AD9265 is a 16-bit, 125 MSPS analog-to-digital converter (ADC). The AD9265 is designed to support communications applications where high performance combined with low cost, small size, and versatility is desired.

The ADC core features a multistage, differential pipelined architecture with integrated output error correction logic to provide 16-bit accuracy at 125 MSPS data rates and guarantees no missing codes over the full operating temperature range.

The ADC features a wide bandwidth differential sample-and-hold analog input amplifier supporting a variety of user-selectable input ranges. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling single-channel inputs at frequencies well beyond the Nyquist rate. Combined with power and cost savings over previously available ADCs, the AD9265 is suitable for applications in communications, instrumentation and medical imaging.

A differential clock input controls all internal conversion cycles. A duty cycle stabilizer provides the means to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance over a wide range of input clock duty cycles. An integrated voltage reference eases design considerations.

The ADC output data format is either parallel 1.8 V CMOS or LVDS (DDR). A data output clock is provided to ensure proper latch timing with receiving logic.

Programming for setup and control is accomplished using a 3-wire SPI-compatible serial interface. Flexible power-down options allow significant power savings, when desired. An optional on-chip dither function is available to improve SFDR performance with low power analog input signals.

The AD9265 is available in a Pb-free, 48-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.

APPLICATIONS

  • Communications
  • Multimode digital receivers (3G)
    • GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, and TD-SCDMA
  • Smart antenna systems
  • General-purpose software radios
  • Broadband data applications
  • Ultrasound equipment

PRODUCT HIGHLIGHTS

  1. On-chip dither option for improved SFDR performance with low power analog input.
  2. Proprietary differential input that maintains excellent SNR performance for input frequencies up to 300 MHz.
  3. Operation from a single 1.8 V supply and a separate digital output driver supply accommodating 1.8 V CMOS or LVDS outputs.
  4. Standard serial port interface (SPI) that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock duty cycle stabilizer, DCS, power-down, test modes, and voltage reference mode.
  5. Pin compatibility with the AD9255, allowing a simple migration from 16 bits down to 14 bits.
Part Models 6
1ku List Price Starting From $63.92

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Documentation

Documentation

Part Model Pin/Package Drawing Documentation CAD Symbols, Footprints, and 3D Models
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AD9265BCPZRL7-105
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Product Lifecycle

PCN

Feb 1, 2024

- 24_0009

Qualification of alternative Wafer Fab for TSMC 0.18um Mixed Signal CMOS Process

AD9265BCPZ-105

PRODUCTION

AD9265BCPZ-125

PRODUCTION

AD9265BCPZ-80

PRODUCTION

AD9265BCPZRL7-105

PRODUCTION

AD9265BCPZRL7-125

PRODUCTION

AD9265BCPZRL7-80

PRODUCTION

Jun 9, 2021

- 20_0126

Conversion of Select Sizes LFCSP Products from Punched to Sawn and Transfer of Assembly Site to ASE Korea

Sep 13, 2017

- 16_0077

CANCELLED: Conversion of Select 4x4, 5x5, 6x6 and 7x7mm LFCSP Package Outlines from Punch to Sawn and Transfer of Assembly Site to ASE Korea.

AD9265BCPZ-105

PRODUCTION

AD9265BCPZ-125

PRODUCTION

AD9265BCPZ-80

PRODUCTION

AD9265BCPZRL7-105

PRODUCTION

AD9265BCPZRL7-125

PRODUCTION

AD9265BCPZRL7-80

PRODUCTION

Filter by Model

reset

Reset Filters

Part Models

Product Lifecycle

PCN

Feb 1, 2024

- 24_0009

arrow down

Qualification of alternative Wafer Fab for TSMC 0.18um Mixed Signal CMOS Process

AD9265BCPZ-105

PRODUCTION

AD9265BCPZ-125

PRODUCTION

AD9265BCPZ-80

PRODUCTION

AD9265BCPZRL7-105

PRODUCTION

AD9265BCPZRL7-125

PRODUCTION

AD9265BCPZRL7-80

PRODUCTION

Jun 9, 2021

- 20_0126

arrow down

Conversion of Select Sizes LFCSP Products from Punched to Sawn and Transfer of Assembly Site to ASE Korea

Sep 13, 2017

- 16_0077

arrow down

CANCELLED: Conversion of Select 4x4, 5x5, 6x6 and 7x7mm LFCSP Package Outlines from Punch to Sawn and Transfer of Assembly Site to ASE Korea.

AD9265BCPZ-105

PRODUCTION

AD9265BCPZ-125

PRODUCTION

AD9265BCPZ-80

PRODUCTION

AD9265BCPZRL7-105

PRODUCTION

AD9265BCPZRL7-125

PRODUCTION

AD9265BCPZRL7-80

PRODUCTION

Software & Part Ecosystem

Software & Part Ecosystem

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Evaluation Kit

Evaluation Kits 2

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SDP-H1

High Speed Controller Board

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SDP-H1

High Speed Controller Board

High Speed Controller Board

Features and Benefits

  • Xilinx® Spartan 6
  • 1 x FMC Low Pin Count ( LPC) connector
  • LVDS and single ended LVCMOS signaling
  • DDR2
  • JTAG header
  • Blackfin processor ADSP-BF527
  • 1 x small Footprint 120 pin connector
  • Configurable Peripheral Interfaces SPI, SPORT, I2C, GPIO, Asynchronous Parallel, PPI, Timers
  • USB 2.0 interface to the PC

Product Detail

The SDP-H1 is a high speed controller board for the System Demonstration Platform (SDP). The SDP-H1 has a Xilinx® Spartan 6 and an ADSP-BF527 processor with connectivity to the PC through a USB 2.0 high speed port. Controller boards allow for the configuration and capture of data on daughter boards from the PC via USB.

The SDP-H1 has a FMC low pin count ( LPC) connector with full differential LVDS and singled ended LVCMOS support. It also has the 120 pin connector, found on the SDP-B which exposes the Blackfin processors peripherals. This connector provides a configurable Serial, Parallel I2C and SPI and GPIO communications lines to the attached daughter board. The PC side software application for controlling the attached daughter board is provided with each of the daughter product evaluation boards or Circuits from the Lab reference Circuits.

The System Demonstration Platform is a collection of controller boards, interposer boards, and daughter boards, used for easy, low cost evaluation of ADI components and reference circuits. For a general overview of the entire platform visit the System Demonstration Platform homepage www.analog.com/sdp

See the full list of compatible Product Evaluation Boards and Circuits from the Lab Reference Circuit Boards that require the SDP-B. All SDP-S compatible daughter boards can be used with the SDP-B.

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EVAL-AD9265

AD9265 Evaluation Board

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EVAL-AD9265

AD9265 Evaluation Board

AD9265 Evaluation Board

Features and Benefits

  • Full featured evaluation board for the AD9265
  • SPI interface for setup and control
  • External, on-board oscillator, and AD9517 clocking options
  • Balun/transformer or amplifier input drive option
  • LDO regulator or switching power supply options
  • VisualAnalog® and SPI controller software interfaces

Product Detail

This page contains evaluation board documentation and ordering information for evaluating the AD9265.

The AD9265-FMC-125EBZ is an evaluation board for the AD9265, single, 16-bit ADC. This reference design provides all of the support circuitry to operate devices in their various modes and configurations, It is designed to interface directly with the EVAL-SDP-CH1Z data capture card, allowing users to download captured data for analysis. The Visual Analog software package, which is used to interface with the device’s hardware, allows users to download captured data for analysis with a user-friendly graphical interface. The SPI controller software package is also compatible with this hardware and allows the user to access the SPI programmable features of the AD9265.

The AD9265 data sheet provides additional information related to device configuration and performance and should be consulted when using these tools. All documents and Visual Analog and SPI Controller are available at the System Demonstration Platform (SDP) page. For additional information or questions, please email highspeedproductssupport@analog.com.

Tools & Simulations

Tools & Simulations 6

Reference Designs

Reference Designs 1

High Speed, Single-Ended-to-Differential ADC Driver

Single-Supply DC-Coupled 16-Bit, 125 MSPS Analog Front End for Bipolar Input

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