AD6641

RECOMMENDED FOR NEW DESIGNS

AD6641

250 MHz Bandwidth DPD Observation Receiver

RECOMMENDED FOR NEW DESIGNS

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Part Models 2

1ku List Price Starting From $160.44

Features

SNR = 65.8 dBFS at f_IN up to 250 MHz at 500 MSPS
ENOB of 10.5 bits at f_IN up to 250 MHz at 500 MSPS (−1.0 dBFS)
SFDR = 80 dBc at f_IN up to 250 MHz at 500 MSPS (−1.0 dBFS)
Excellent linearity
- DNL = ±0.5 LSB typical, INL = ±0.6 LSB typical
Integrated 16k × 12 FIFO
FIFO readback options
- 12-bit parallel CMOS at 62.5 MHz
- 6-bit DDR LVDS interface
- SPORT at 62.5 MHz
- SPI at 25 MHz

High speed synchronization capability
1 GHz full power analog bandwidth
Integrated input buffer
On-chip reference, no external decoupling required
Low power dissipation
- 695 mW at 500 MSPS
- Programmable input voltage range
- 1.18 V to 1.6 V, 1.5 V nominal
1.9 V analog and digital supply operation
1.9 V or 3.3 V SPI and SPORT operation
Clock duty cycle stabilizer
Integrated data clock output with programmable clock and data alignment

Additional Details

The AD6641 is a 250 MHz bandwidth digital predistortion (DPD) observation receiver that integrates a 12-bit 500 MSPS ADC, a 16k × 12 FIFO, and a multimode back end that allows users to retrieve the data through a serial port (SPORT), the SPI interface, a 12-bit parallel CMOS port, or a 6-bit DDR LVDS port after being stored in the integrated FIFO memory. It is optimized for outstanding dynamic performance and low power consumption and is suitable for use in telecommunications applications such as a digital predistortion observation path where wider bandwidths are desired. All necessary functions, including the sample-and-hold and voltage reference, are included on the chip to provide a complete signal conversion solution.

The on-chip FIFO allows small snapshots of time to be captured via the ADC and read back at a lower rate. This reduces the constraints of signal processing by transferring the captured data at an arbitrary time and at a much lower sample rate. The FIFO can be operated in several user-programmable modes. In the single capture mode, the ADC data is captured when signaled via the SPI port or the use of the external FILL± pins. In the continuous capture mode, the data is loaded continuously into the FIFO and the FILL± pins are used to stop this operation.

The data stored in the FIFO can be read back based on several user-selectable output modes. The DUMP pin can be asserted to output the FIFO data. The data stored in the FIFO can be accessed via a SPORT, SPI, 12-bit parallel CMOS port, or 6-bit DDR LVDS interface. The maximum output throughput supported by the AD6641 is in the 12-bit CMOS or 6-bit DDR LVDS mode and is internally limited to 1/8th of the maximum input sample rate. This corresponds to the maximum output data rate of 62.5 MHz at an input clock rate of 500 MSPS.

The ADC requires a 1.9 V analog voltage supply and a differential clock for full performance operation. Output format options include twos complement, offset binary format, or Gray code. A data clock output is available for proper output data timing. Fabricated on an advanced SiGe BiCMOS process, the device is available in a 56-lead LFCSP and is specified over the industrial temperature range (−40°C to +85°C). This product is protected by a U.S. patent.

Applications

Wireless and wired broadband communications
Communications test equipment
Power amplifier linearization

Product Highlights

High Performance ADC Core.
Maintains 65.8 dBFS SNR at 500 MSPS with a 250 MHz input.
Low Power. Consumes only 695 mW at 500 MSPS.
Ease of Use.
On-chip 16k FIFO allows the user to target the high performance ADC to the time period of interest and reduce the constraints of processing the data by transferring it at an arbitrary time and a lower sample rate. The on-chip reference and sample-and-hold provide flexibility in system design. Use of a single 1.9 V supply simplifies system power supply design.
Serial Port Control.
Standard serial port interface supports configuration of the device and customization for the user’s needs.
1.9 V or 3.3 V SPI and Serial Data Port Operation.

View All Documentation

Ask a Question

Submit your question below and we will return the best answer from ADI’s knowledge database:

Other places you can find help

Support

Analog Devices Support Portal is a one-stop shop to answer all your ADI questions.

Visit the ADI Support Page

Ask the ADI community for help.

Ask the EngineerZone Community

FAQs

Sales & Ordering FAQs

Part Models 2

1ku List Price Starting From $160.44

Documentation

Technical Documents 13

AD6641: 250 MHz Bandwidth DPD Observation Receiver Data Sheet (Rev.A) 04/19/2011

UG-292: Evaluating the AD6641 DPD Observation Receiver 07/21/2011

AN-807: Multicarrier WCDMA Feasibility (Rev.0) 11/09/2007

AN-808: Multicarrier CDMA2000 Feasibility (Rev.0) 11/09/2007

AN-586: LVDS Outputs for High Speed A/D Converters (Rev.0) 02/14/2015

AN-878: High Speed ADC SPI Control Software (Rev.A) 03/20/2018

AN-877: Interfacing to High Speed ADCs via SPI (Rev.B) 11/09/2007

AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev.0) 02/14/2015

AN-827: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs (Rev.0) 02/14/2015

AN-835: Understanding High Speed ADC Testing and Evaluation 07/01/2020

AN-1142: Techniques for High Speed ADC PCB Layout 01/12/2012

AN-905: VisualAnalog™ Converter Evaluation Tool Version 1.0 User Manual 08/18/2020

AN-935: Designing an ADC Transformer-Coupled Front End 09/01/2007

Design Resources 2

ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.

Part Model	Pin/Package Drawing	Documentation	CAD Symbols, Footprints, and 3D Models
AD6641BCPZ-500	56 ld LFCSP (8x8mm)	HTML Material Declaration HTML Reliablity Data	Ultra Librarian SamacSys
AD6641BCPZRL7-500	56 ld LFCSP (8x8mm)	HTML Material Declaration HTML Reliablity Data	Ultra Librarian SamacSys

AD6641BCPZ-500
Pin/Package Drawing
56 ld LFCSP (8x8mm)
Documentation

HTML Material Declaration

HTML Reliablity Data

CAD Symbols, Footprints, and 3D Models
Ultra Librarian
SamacSys

AD6641BCPZRL7-500
Pin/Package Drawing
56 ld LFCSP (8x8mm)
Documentation

HTML Material Declaration

HTML Reliablity Data

CAD Symbols, Footprints, and 3D Models
Ultra Librarian
SamacSys

PCN/PDN Information

Filter by Model

Part Models

Product Lifecycle

PCN

Jun 9, 2021

- 20_0126

Conversion of Select Sizes LFCSP Products from Punched to Sawn and Transfer of Assembly Site to ASE Korea

AD6641BCPZ-500

PRODUCTION

AD6641BCPZRL7-500

PRODUCTION

pdf

PCN20_0126_Form

pdf

Qualification Results Summary

xls

Material_Report

pdf

Detailed Change Description

pdf

Package Outline Drawing

pdf

Package Outline Drawing

pdf

Qualification Results Summary

pdf

Qualification Results Summary

pdf

Qualification Results Summary

pdf

Qualification Results Summary

Filter by Model

Part Models

Product Lifecycle

PCN

Jun 9, 2021

- 20_0126

Conversion of Select Sizes LFCSP Products from Punched to Sawn and Transfer of Assembly Site to ASE Korea

AD6641BCPZ-500

PRODUCTION

AD6641BCPZRL7-500

PRODUCTION

pdf

PCN20_0126_Form

pdf

Qualification Results Summary

xls

Material_Report

pdf

Detailed Change Description

pdf

Package Outline Drawing

pdf

Package Outline Drawing

pdf

Qualification Results Summary

pdf

Qualification Results Summary

pdf

Qualification Results Summary

pdf

Qualification Results Summary

Software & Part Ecosystem

Companion Parts 13

Parts	Product Life Cycle	Description
Clock Distribution Devices3
AD9513	RECOMMENDED FOR NEW DESIGNS	800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs
AD9514	RECOMMENDED FOR NEW DESIGNS	1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs
AD9515	RECOMMENDED FOR NEW DESIGNS	1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs
Clock Generation Devices5
AD9510	RECOMMENDED FOR NEW DESIGNS	1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs
AD9511	RECOMMENDED FOR NEW DESIGNS	1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs
AD9512	RECOMMENDED FOR NEW DESIGNS	1.2 GHz Clock Distribution IC, Two 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs
AD9523	NOT RECOMMENDED FOR NEW DESIGNS	14-Output, Low Jitter Clock generator
AD9524	NOT RECOMMENDED FOR NEW DESIGNS	6 Output, Dual Loop Clock Generator
Digital Control VGAs2
ADL5202	Obsolete	Wide Dynamic Range, High Speed, Digitally Controlled VGA
AD8376	RECOMMENDED FOR NEW DESIGNS	Ultralow Distortion IF Dual VGA
Fully Differential Amplifiers1
ADL5562	RECOMMENDED FOR NEW DESIGNS	3.3 GHz Ultralow Distortion RF/IF Differential Amplifier
Single-Ended to Differential Amplifiers2
ADA4927-2	RECOMMENDED FOR NEW DESIGNS	Ultralow Distortion Current Feedback Differential ADC Driver
ADA4938-2	RECOMMENDED FOR NEW DESIGNS	Ultralow Distortion Differential ADC Driver (Dual)

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Evaluation Kit

EVAL-AD6641

AD6641 Evaluation Board

EVAL-AD6641

AD6641 Evaluation Board

Features and Benefits

Full featured evaluation board for the AD6641
SPI interface for setup and control
External, on-board oscillator or AD9517 clocking options
Balun/transformer or amplifier input drive options
LDO regulator or switching power supply options
VisualAnalog and SPI controller software interfaces

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Product Detail

This page contains evaluation board documentation and ordering information for evaluating the AD6641.

Resources

pdf

UG-292: Evaluating the AD6641 DPD Observation Receiver

1635 kB

HSC-ADC-EVALCZ

FPGA-Based Data Capture Kit

HSC-ADC-EVALCZ

FPGA-Based Data Capture Kit

Features and Benefits

64kB FIFO Depth
Works with single and multi-channel ADCs
Use with VisualAnalog^® software
Based on Virtex-4 FPGA
May require adaptor to interface with some ADC eval boards
Allows programming of SPI control Up to 644 MSPS SDR / 800MSPS DDR Encode Rates on each channel
DDR Encode Rates on each channel

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Product Detail

The HSC-ADC-EVALCZ high speed converter evaluation platform uses an FPGA based buffer memory board to capture blocks of digital data from the Analog Devices high speed analog-to-digital converter (ADC) evaluation boards. The board is connected to the PC through a USB port and is used with VisualAnalog^® to quickly evaluate the performance of high speed ADCs. The evaluation kit is easy to set up. Additional equipment needed includes an Analog Devices high speed ADC evaluation board, a signal source, and a clock source. Once the kit is connected and powered, the evaluation is enabled instantly on the PC.

Resources

PDF

High Speed ADC USB FPGA Evaluation Kit, EVALC

2.1 M

Software

ZIP

High Speed ADC SPI Control Software

29.79 M

ZIP

EVALC PC Board Gerber File

ZIP

Microsoft .NET Framework 3.5

EVAL-AD6641

AD6641 Evaluation Board

HSC-ADC-EVALCZ

FPGA-Based Data Capture Kit

Tools & Simulations

IBIS Model 1

Simulation Model

IBIS Model

AD6641BCPZ (Valid for all Speeds)

Visual Analog

For designers who are selecting or evaluating high speed ADCs, VisualAnalog™ is a software package that combines a powerful set of simulation and data analysis tools with a user-friendly graphical interface.

Open Tool