Considerations on High-Speed Converter PCB Design, Part 1: Power and Ground Planes.


What are some important PCB layout rules when using a high-speed converter?

RAQ:  Issue 63


To ensure that the design meets datasheet specifications, you should follow a few guidelines. First, an age old question: "Should the AGND and DGND ground planes be split?" The short answer is: it depends.

The long answer is: not usually. Why? In most situations a split ground plane can cause more harm than good, as splitting the ground plane only serves to increase the inductance for the return current. Remember the equation V = L(di/dt)? As the inductance increases, so does the voltage noise. As the switching current increases–and it will as converter sampling rates increase–the voltage noise will also increase. Therefore, keep the grounds connected unless you have a reason to split them.

One example is when a form factor restriction prohibits good layout partitioning. This could be because the dirty bus supplies or digital circuits must be located in certain areas to conform with legacy designs. In that case, splitting the ground plane may make the difference in achieving good performance. However, to make the overall design work, a bridge or tie point is required to connect the grounds together somewhere on the board. With that being the case, spread the tie points evenly across the ground plane split. One tie point on the PCB often ends up being the optimum place for the return current to pass without reducing performance. This tie point is usually near or under the converter.

When designing the power planes, use all of the copper available for these designated layers. If possible, don't share traces on the same layers, as additional traces and vias can quickly compromise the power plane by breaking it into smaller pieces. The resultant sparse plane can squeeze current paths down where they are needed most: at the converter's supply pins. Squeezing currents between vias and traces increases resistance and can cause slight drops in voltage at the converter's supply pins.

Finally, placement of power planes is critical–don’t overlay the noisy digital plane over the analog plane, as they can still couple even if they are on different layers. To reduce the risk of degrading system performance, keep these types of planes separated and non-overlapping throughout each layer in the design if possible.

Stay tuned for Part 2, where power delivery and decoupling high-speed converters will be discussed.


Rob Reeder

Rob Reeder

Rob Reeder was a senior system application engineer with Analog Devices Inc. in the High Speed Converter and RF Applications Group in Greensboro, NC. He has published numerous papers on converter interfaces, converter testing, and analog signal chain design for a variety of applications. Formerly, Rob was an applications engineer for the Aerospace and Defense Group for five years focusing on a variety of radar, EW, and instrumentation applications, and he was part of the high speed converter product line for nine years. His prior experience also includes test development and analog design engineer for the Multichip Products Group at ADI, designing analog signal chain modules for space, military, and high reliability applications for five years. Rob received his M.S.E.E. and B.S.E.E. degrees from Northern Illinois University in DeKalb, Ill., in 1998 and 1996, respectively.