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  5. AD9517-2


Features and Benefits

  • Low phase noise, phase-locked loop (PLL)
    On-chip VCO tunes from 2.05 GHz to 2.33 GHz
  • External VCO/VCXO to 2.4 GHz optional
  • 1 differential or 2 single-ended reference inputs
  • Reference monitoring capability
  • Automatic revertive and manual reference
    switchover/holdover modes
  • Accepts LVPECL, LVDS, or CMOS references to 250 MHz
  • Programmable delays in path to PFD
  • Digital or analog lock detect, selectable
  • Each LVDS output can be reconfigured as two 250 MHz CMOS outputs
  • 2 pairs of 1.6 GHz LVPECL outputs
    Each output pair shares a 1-to-32 divider with coarse phase delay
    Additive output jitter: 225 fs rms
    Channel-to-channel skew paired outputs of <10 ps
  • 2 pairs of 800 MHz LVDS clock outputs
    Each output pair shares two cascaded 1-to-32 dividers with coarse phase delay
    Additive output jitter: 275 fs rms
    Fine delay adjust (Δt) on each LVDS output
  • Automatic synchronization of all outputs on power-up
  • Manual output synchronization available
  • Available in a 48-lead LFCSP

Product Details

The AD9517-21 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 2.05 GHz to 2.33 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz can be used.

The AD9517-2 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements.

The AD9517-2 features four LVPECL outputs (in two pairs) and four LVDS outputs (in two pairs). Each LVDS output can be reconfigured as two CMOS outputs. The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz.

For applications that require additional outputs, a crystal reference input, zero-delay, or EEPROM for automatic configuration at startup, the AD9520 and AD9522 are available. In addition, the AD9516 and AD9518 are similar to the AD9517 but have a different combination of outputs.

Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow a range of divisions up to a maximum of 1024.

The AD9517-2 is available in a 48-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5 V. A separate LVPECL power supply can be from 2.5 V to 3.3 V (nominal).

The AD9517-2 is specified for operation over the industrial range of −40°C to +85°C.


  • Low jitter, low phase noise clock distribution
  • 10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4
  • Forward error correction (G.710)
  • Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
  • High performance wireless transceivers
  • ATE and high performance instrumentation

1 AD9517 is used throughout to refer to all the members of the AD9517 family. However, when AD9517-2 is used, it is refers to that specific member of the AD9517 family.

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This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.

Evaluation Kits (1)

Documentation & Resources

  • View All (37)
  • Evaluation Design File (3)
  • Data Sheet (1)
  • Application Note (11)
  • User Guide (1)
  • Demo Board Schematic (1)
  • Frequently Asked Question (1)
  • Product Selection Guide (1)
  • Technical Article (6)
  • Rarely Asked Question (12)
  • Application Note
    Frequently Asked Question
    Rarely Asked Question

    Tools & Simulations

    IBIS Model

    AD9517-x IBIS Models

    Design Tool

    ADIsimCLK Design and Evaluation Software

    ADIsimCLK is the design tool developed specifically for Analog Devices' range of ultra-low jitter clock distribution and clock generation products. Whether your application is in wireless infrastructure, instrumentation, networking, broadband, ATE or other areas demanding predictable clock performance, ADIsimCLK will enable you to rapidly develop, evaluate and optimize your design.

    Product Recommendations

    AD9517-2 Companion Parts

    Recommended Reference Buffer

    Recommended Reference Clean Up PLL

    Design Resources

    ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well.  "Zero defects" for shipped products is always our goal.View our quality and reliability program and certifications for more information.

    Part Number Material Declaration Reliability Data Pin/Package Drawing CAD Symbols, Footprints & 3D Models
    AD9517-2ABCPZ Material Declaration Reliability Data 48-Lead LFCSP (7mm x 7mm x 0.85mm w/ EP)
    AD9517-2ABCPZ-RL7 Material Declaration Reliability Data 48-Lead LFCSP (7mm x 7mm x 0.85mm w/ EP)
    AD9517-2BCPZ Material Declaration Reliability Data 48-Lead LFCSP (7mm x 7mm w/ EP)
    AD9517-2BCPZ-REEL7 Material Declaration Reliability Data 48-Lead LFCSP (7mm x 7mm w/ EP)
    Wafer Fabrication Data

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