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AD9520-5: 12 LVPECL/24 CMOS Output Clock Generator Data Sheet (Rev. B)9/26/2008PDF1 M
Overview
Features and Benefits
- Low phase noise, phase-locked loop (PLL)
- Optional external 3.3 V/5 V VCO/VCXO to 2.4 GHz
- 1 differential or 2 single-ended reference inputs
- Accepts CMOS, LVDS, or LVPECL references to 250 MHz
- Accepts 16.62 MHz to 33.3 MHz crystal for reference input
- Optional reference clock doubler
- Reference monitoring capability
- Automatic/ manual reference holdover and reference switchover modes, with revertive switching
- Glitch-free switchover between references
- Automatic recovery from holdover
- Digital or analog lock detect, selectable
- Optional zero delay operation
- Twelve 1.6 GHz LVPECL outputs divided into 4 groups
- Each group of 3 outputs shares a 1-to-32 divider with phase delay
- Additive output jitter as low as 225 fs rms
- Channel-to-channel skew grouped outputs < 16 ps
- Each LVPECL output can be configured as 2 CMOS outputs (for fOUT ≤ 250 MHz)
- Automatic synchronization of all outputs on power-up
- Manual output synchronization available
- SPI- and I2C-compatible serial control port
- 64-lead LFCSP
- Nonvolatile EEPROM stores configuration settings
Product Details
The AD9520-5 provides a multioutput clock distribution function with subpicosecond jitter performance, along with an on-chip PLL that can be used with an external VCO.
The AD9520-5 serial interface supports both SPI and I2C ports. An in-package EEPROM, which can be programmed through the serial interface, can store user-defined register settings for power-up and chip reset.
The AD9520-5 features 12 LVPECL outputs in four groups. Any of the 1.6 GHz LVPECL outputs can be reconfigured as two 250 MHz CMOS outputs. If an application requires LVDS drivers instead of LVPECL drivers, refer to the AD9522-5. Each group of three outputs has a divider that allows both the divide ratio (from 1 to 32) and the phase offset or coarse time delay to be set.
The AD9520-5 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. The external VCO can have an operating voltage of up to 5.5 V. A separate output driver power supply can be from 2.375 V to 3.465 V.
The AD9520-5 is specified for operation over the standard industrial range of −40°C to +85°C.
Applications
- Low jitter, low phase noise clock distribution
- Clock generation and translation for SONET, 10Ge, 10GFC, Synchronous Ethernet, OTU2/3/4
- Forward error correction (G.710)
- Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
- High performance wireless transceivers
- ATE and high performance instrumentation
- Broadband infrastructures
Product Categories
Product Lifecycle
Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (1)
Documentation & Resources
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AN-1580: Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (Rev. B)9/4/2018PDF382 K
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AN-0983: Introduction to Zero-Delay Clock Timing Techniques2/14/2015PDF162 kB
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UG-076: AD9520-x Evaluation Board User Guide (Rev. A)2/1/2010PDF1 M
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AD9520 Schematic (Rev. B)9/17/2013PDF488 K
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AD9520 Schematic (Rev. A)6/8/2010PDF94 K
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FAQs7/26/2017
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RF, Microwave, and Millimeter Wave Product Selection Guide7/13/2018PDF9M
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CN-0186: Phase Coherent FSK Modulator1/11/2011PDF239 kB
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Resolution vs. ENOB – Still Hazy After All These Years2/1/2013
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Considerations on High-Speed Converter PCB Design, Part 4: Plane Coupling2/1/2012
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Crosstalkin’ Converters11/1/2011
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Balancing Phase in High-Speed Converters8/1/2011
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Considerations on High-Speed Converter PCB Design, Part 3: The E-Pad Low Down5/1/2011
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Considerations on High-Speed Converter PCB Design, Part 2: Power and Ground Planes.2/1/2011
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Considerations on High-Speed Converter PCB Design, Part 1: Power and Ground Planes.11/1/2010
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Watch for Those Multiple Clocking Edges!8/1/2010
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Taming A/D Converter Power Supplies3/1/2010
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What’s the (Converter) Frequency Kenneth?9/1/2009
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Keeping Common Modes Common4/1/2009
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Are Your Filters Filtering?2/1/2009
Tools & Simulations
Design Tools
ADIsimCLK Design and Evaluation Software
ADIsimCLK is the design tool developed specifically for Analog Devices' range of ultra-low jitter clock distribution and clock generation products. Whether your application is in wireless infrastructure, instrumentation, networking, broadband, ATE or other areas demanding predictable clock performance, ADIsimCLK will enable you to rapidly develop, evaluate and optimize your design.
Reference Designs (1)
Design Resources
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.View our quality and reliability program and certifications for more information.
| Part Number | Material Declaration | Reliability Data | Pin/Package Drawing | CAD Symbols, Footprints & 3D Models |
|---|---|---|---|---|
| AD9520-5BCPZ | Material Declaration | Reliability Data | 64-Lead LFCSP (9mm x 9mm w/ EP) | |
| AD9520-5BCPZ-REEL7 | Material Declaration | Reliability Data | 64-Lead LFCSP (9mm x 9mm w/ EP) | |
| Wafer Fabrication Data |
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Sample & Buy
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Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.