AD9520-0
Info : RECOMMENDED FOR NEW DESIGNS
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AD9520-0

12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.8 GHz VCO

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Info : RECOMMENDED FOR NEW DESIGNS tooltip
Info : RECOMMENDED FOR NEW DESIGNS tooltip
Part Details
Part Models 2
1ku List Price Starting From $16.03
Features
  • Low phase noise, phase-locked loop (PLL)
    • On-chip VCO tunes from 2.53 GHz to 2.95 GHz
    • Optional external 3.3 V/5 V VCO/VCXO to 2.4 GHz
    • 1 differential or 2 single-ended reference inputs
    • Accepts CMOS, LVDS, or LVPECL references to 250 MHz
    • Accepts 16.62 MHz to 33.3 MHz crystal for reference input
    • Optional reference clock doubler
    • Reference monitoring capability
    • Automatic/manual reference holdover and reference switchover modes, with revertive switching
    • Glitch-free switchover between references
    • Automatic recovery from holdover
    • Digital or analog lock detect, selectable
    • Optional zero delay operation
  • Twelve 1.6 GHz LVPECL outputs divided into 4 groups
    • Each group of 3 outputs shares a 1-to-32 divider with phase delay
    • Additive output jitter as low as 225 fs rms
    • Channel-to-channel skew grouped outputs < 16 ps
    • Each LVPECL output can be configured as 2 CMOS outputs (for fOUT ≤ 250 MHz)
  • Automatic synchronization of all outputs on power-up
  • Manual output synchronization available
  • SPI- and I2C-compatible serial control port
  • 64-lead LFCSP
  • Nonvolatile EEPROM stores configuration settings
Additional Details
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The AD9520-0 provides a multi-output clock distribution function with sub-picosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 2.53 GHz to 2.95 GHz. An external 3.3 V/5 V VCO/VCXO of up to 2.4 GHz can also be used.

The AD9520-0 serial interface supports both SPI and I2C ports. An in-package EEPROM, which can be programmed through the serial interface, can store user-defined register settings for power-up and chip reset.

The AD9520-0 features 12 LVPECL outputs in four groups. Any of the 1.6 GHz LVPECL outputs can be reconfigured as two 250 MHz CMOS outputs. If an application requires LVDS drivers instead of LVPECL drivers, refer to the AD9522-0.

Each group of three outputs has a divider that allows both the divide ratio (from 1 to 32) and the phase offset or coarse time delay to be set.

The AD9520-0 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. The external VCO can have an operating voltage of up to 5.5 V. A separate output driver power supply can be from 2.375 V to 3.465 V.

The AD9520-0 is specified for operation over the standard industrial range of −40°C to +85°C.

Applications

  • Low jitter, low phase noise clock distribution
  • Clock generation and translation for SONET, 10Ge, 10GFC, Synchronous Ethernet, OTU2/3/4
  • Forward error correction (G.710)
  • Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
  • High performance wireless transceivers
  • ATE and high performance instrumentation
  • Broadband infrastructures
Part Models 2
1ku List Price Starting From $16.03

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Documentation

Documentation

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Part Model Pin/Package Drawing Documentation CAD Symbols, Footprints, and 3D Models
AD9520-0BCPZ
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AD9520-0BCPZ-REEL7
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Product Lifecycle

PCN

Jun 26, 2023

- 23_0025

Package Outline Drawing and Data Sheet Revision for Select LFCSP Products in Amkor

Nov 7, 2016

- 16_0168

AD9520 Power Dissipation in Power Down spec change

AD9520-0BCPZ

PRODUCTION

AD9520-0BCPZ-REEL7

PRODUCTION

Filter by Model

reset

Reset Filters

Part Models

Product Lifecycle

PCN

Jun 26, 2023

- 23_0025

arrow down

Package Outline Drawing and Data Sheet Revision for Select LFCSP Products in Amkor

Nov 7, 2016

- 16_0168

arrow down

AD9520 Power Dissipation in Power Down spec change

AD9520-0BCPZ

PRODUCTION

AD9520-0BCPZ-REEL7

PRODUCTION

Software and Part Ecosystem

Software and Part Ecosystem

Evaluation Kit

Evaluation Kits 1

EVAL-AD9520-0

AD9520-0 Evaluation Board

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EVAL-AD9520-0

AD9520-0 Evaluation Board

AD9520-0 Evaluation Board

Features and Benefits

  • Simple power connection using 6 V wall adapter and on-board LDO voltage regulators
  • LDOs are easily bypassed for power measurements
  • 5 ac-coupled differential LVPECL SMA connectors
  • 7 LVPECL differential headers for additional outputs
  • SMA connectors for
    2 reference inputs
    Charge pump output
    Clock distribution input
  • USB connection to PC
  • Microsoft Windows-based evaluation software with simple graphical user interface
  • On-board PLL loop filter
  • Easy access to digital I/O and diagnostic signals via
  • I/O header
  • Status LEDs for diagnostic signals

Product Detail

The AD9520-x (hereafter referred to as AD9520) is a very low noise PLL clock synthesizer featuring an integrated VCO, clock dividers, and up to 24 outputs. The AD9520 features automatic holdover and a flexible reference input circuit allowing for very smooth reference clock switching. The AD9520 family also features the necessary provisions for an external VCXO.

The AD9520 evaluation board is a compact, easy-to-use platform for evaluating all features of the AD9520.

Tools & Simulations

Tools & Simulations 2

Reference Designs

Reference Designs 1

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