Features and Benefits
- Low phase noise, phase-locked loop (PLL)
- On-chip VCO tunes from 2.05 GHz to 2.33 GHz
- External VCO/VCXO to 2.4 GHz optional
- 1 differential or 2 single-ended reference inputs
- Reference monitoring capability
- Automatic revertive and manual reference switchover/holdover modes
- Accepts LVPECL, LVDS, or CMOS references to 250 MHz
- Programmable delays in path to PFD
- Digital or analog lock detect, selectable
- 3 pairs of 1.6 GHz LVPECL outputs
- Each output pair shares a 1-to-32 divider with coarse phase delay
- Additive output jitter: 225 fs rms
- Channel-to-channel skew paired outputs of <10 ps
- Automatic synchronization of all outputs on power-up
- Manual output synchronization available
- Available in a 48-lead LFCSP
The AD9518-21 The AD9518-21 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 2.05 GHz to 2.33 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz can be used.
The AD9518-2 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements.
The AD9518-2 features six LVPECL outputs (in three pairs). The LVPECL outputs operate to 1.6 GHz.
For applications that require additional outputs, a crystal reference input, zero-delay, or EEPROM for automatic configuration at startup, the AD9520 and AD9522 are available.
In addition, the AD9516 and AD9517 are similar to the AD9518 but have a different combination of outputs.
Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division for the LVPECL outputs is 1 to 32.
The AD9518-2 is available in a 48-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5 V. A separate LVPECL power supply can be from 2.5 V to 3.3 V (nominal).
The AD9518-2 is specified for operation over the industrial range of −40°C to +85°C.
- Low jitter, low phase noise clock distribution
- 10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4
- Forward error correction (G.710)
- Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
- High performance wireless transceivers
- ATE and high performance instrumentation
1AD9518 is used throughout the data sheet to refer to all the members of the AD9518 family. However, when AD9518-2 is used, it refers to that specific member of the AD9518 family.
Product Lifecycle Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (1)
The AD9516-x, AD9517-x, and AD9518-x are very low noise PLL clock synthesizers featuring an integrated VCO, clock dividers, and up to 14 outputs. The AD9516 features automatic holdover and a flexible reference input circuit allowing for very smooth reference clock switching. The AD9516 family also features the necessary provisions for an external VCXO.
The AD9516 evaluation board is a compact, easy-to-use platform for evaluating all features of the AD9516. The AD9516, AD9517, and AD9518 differ only in package size, and the number of outputs. The evaluation software main window for the AD9517 and AD9518 reflects fewer outputs, but the operation is identical for all devices.
Use the user guide in conjunction with the AD9516, AD9517, and AD9518 data sheets.
Features & Benefits
- Simple power connection using 6 V wall adapter and on-board LDO voltage regulators
- LDOs are easily bypassed for power measurements
- 8 ac-coupled differential LVPECL SMA connectors
- 2 ac-coupled LVPECL differential headers
- 2 dc-coupled differential LVDS SMA connectors that are reconfigurable to four CMOS SMA connectors
- 2 dc-coupled LVDS differential headers that are reconfigurable to four CMOS connectors
- SMA connectors for
2 reference inputs
Charge pump output
Clock distribution input
- USB connection to PC
- Microsoft Windows-based evaluation software with simple graphical user interface
- On-board PLL loop filter
- Easy access to digital I/O and diagnostic signals via I/O header
- Status LEDs for diagnostic signals
Documentation & Resources
AN-835: Understanding High Speed ADC Testing and Evaluation (Rev. B)5/12/2015985 kB
AN-501: Aperture Uncertainty and ADC System Performance (Rev. A)2/14/2015227 K
AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev. 0)2/14/2015291K
AN-769: Generating Multiple Clock Outputs from the AD9540 (Rev. 0)2/14/20150
AN-939: Super-Nyquist Operation of the AD9912 Yields a High RF Output Signal (Rev. 0)2/14/2015221 kB
AN-837: DDS-Based Clock Jitter Performance vs. DAC Reconstruction Filter Performance (Rev. 0)2/14/2015313 kB
AN-823: Direct Digital Synthesizers in Clocking Applications Time (Rev. 0)2/14/2015115 kB
AN-927: Determining if a Spur is Related to the DDS/DAC or to Some Other Source (For Example, Switching Supplies) (Rev. 0)2/14/2015170 kB
AN-0974: Multicarrier TD-SCMA Feasibility3/2/2010634 kB
AN-873: Lock Detect on the ADF4xxx Family of PLL Synthesizers (Rev. 0)12/6/2006207 kB
AN-741: Little Known Characteristics of Phase Noise (Rev. 0)11/29/20041679 kB
UG-075: AD9516-x, AD9517-x, and AD9518-x Evaluation Board User Guide1/30/20101089 kB
RF, Microwave, and Millimeter Wave Product Selection Guide7/13/20189M
Low-power direct digital synthesizer cores enable high level of integration2/20/2008
Improved DDS Devices Enable Advanced Comm Systems9/1/2006
ADI Buys Korean Mobile TV Chip Maker6/7/2006
Design A Clock-Distribution Strategy With Confidence4/27/2006
Understand the Effects of Clock Jitter and Phase Noise on Sampled Systems12/7/2004
Speedy A/Ds Demand Stable Clocks3/22/2004
Resolution vs. ENOB – Still Hazy After All These Years2/1/2013
Considerations on High-Speed Converter PCB Design, Part 4: Plane Coupling2/1/2012
Balancing Phase in High-Speed Converters8/1/2011
Considerations on High-Speed Converter PCB Design, Part 3: The E-Pad Low Down5/1/2011
Considerations on High-Speed Converter PCB Design, Part 2: Power and Ground Planes.2/1/2011
Considerations on High-Speed Converter PCB Design, Part 1: Power and Ground Planes.11/1/2010
Watch for Those Multiple Clocking Edges!8/1/2010
Taming A/D Converter Power Supplies3/1/2010
What’s the (Converter) Frequency Kenneth?9/1/2009
Keeping Common Modes Common4/1/2009
Are Your Filters Filtering?2/1/2009
Tools & Simulations
AD9587-x IBIS Models
ADIsimCLK is the design tool developed specifically for Analog Devices' range of ultra-low jitter clock distribution and clock generation products. Whether your application is in wireless infrastructure, instrumentation, networking, broadband, ATE or other areas demanding predictable clock performance, ADIsimCLK will enable you to rapidly develop, evaluate and optimize your design.
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.View our quality and reliability program and certifications for more information.
|Part Number||Material Declaration||Reliability Data||Pin/Package Drawing||CAD Symbols, Footprints & 3D Models|
|AD9518-2ABCPZ||Material Declaration||Reliability Data||48-Lead LFCSP (7mm x 7mm x 0.85mm w/ EP)|
|AD9518-2ABCPZ-RL7||Material Declaration||Reliability Data||48-Lead LFCSP (7mm x 7mm x 0.85mm w/ EP)|
|AD9518-2BCPZ||Material Declaration||Reliability Data||48-Lead LFCSP (7mm x 7mm w/ EP)|
|AD9518-2BCPZ-REEL7||Material Declaration||Reliability Data||48-Lead LFCSP (7mm x 7mm w/ EP)|
|Wafer Fabrication Data|
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