Features and Benefits
- Low phase noise, phase-locked loop
On-chip VCO tunes from 2.55 GHz to 2.95 GHz
- External VCO/VCXO to 2.4 GHz optional
- 1 differential or 2 single-ended reference inputs
- Reference monitoring capability
- 2 pairs of 1.6 GHz LVPECL outputs
Each output pair shares a 1-to-32 divider with coarse phase delay
Additive output jitter: 225 fs rms
Channel-to-channel skew paired outputs of <10 ps
- 2 pairs of 800 MHz LVDS clock outputs
Each output pair shares two cascaded 1-to-32 dividers with coarse phase delay
Additive output jitter: 275 fs rms
Fine delay adjust (Δt) on each LVDS output
- Each LVDS output can be reconfigured as two 250 MHz CMOS outputs
- Automatic synchronization of all outputs on power-up
- See datasheet for additional features
Product DetailsThe AD9517-01 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 2.55 GHz to 2.95 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz can be used.
The AD9517-0 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements.
The AD9517-0 features four LVPECL outputs (in two pairs) and four LVDS outputs (in two pairs). Each LVDS output can be reconfigured as two CMOS outputs. The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz.
For applications that require additional outputs, a crystal reference input, zero-delay, or EEPROM for automatic configuration at startup, the AD9520 and AD9522 are available. In addition, the AD9516 and AD9518 are similar to the AD9517 but have a different combination of outputs.
Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow a range of divisions up to a maximum of 1024.
The AD9517-0 is available in a 48-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5 V. A separate LVPECL power supply can be from 2.5 V to 3.3 V (nominal).The AD9517-0 is specified for operation over the industrial range of −40°C to +85°C.
- Low jitter, low phase noise clock distribution
- 10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4
- Forward error correction (G.710)
- Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
- High performance wireless transceivers
- ATE and high performance instrumentation
1AD9517 is used throughout to refer to all the members of the AD9517 family. However, when AD9517-0 is used, it is referring to that specific member of the AD9517 family.
Product Lifecycle Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (1)
The AD9516-x, AD9517-x, and AD9518-x are very low noise PLL clock synthesizers featuring an integrated VCO, clock dividers, and up to 14 outputs. The AD9516 features automatic holdover and a flexible reference input circuit allowing for very smooth reference clock switching. The AD9516 family also features the necessary provisions for an external VCXO.
The AD9516 evaluation board is a compact, easy-to-use platform for evaluating all features of the AD9516. The AD9516, AD9517, and AD9518 differ only in package size, and the number of outputs. The evaluation software main window for the AD9517 and AD9518 reflects fewer outputs, but the operation is identical for all devices.
For convenience, detailed information from the AD9516 data sheet has been included here. Use the user guide in conjunction with the AD9516, AD9517, and AD9518 data sheets, as well as additional documentation available at www.analog.com.
Features & Benefits
- Simple power connection using 6 V wall adapter and on-board LDO voltage regulators
- LDOs are easily bypassed for power measurements
- 8 ac-coupled differential LVPECL SMA connectors
- 2 ac-coupled LVPECL differential headers
- 2 dc-coupled differential LVDS SMA connectors that are reconfigurable to four CMOS SMA connectors
- 2 dc-coupled LVDS differential headers that are reconfigurable to four CMOS connectors
- SMA connectors for
2 reference inputs
Charge pump output
Clock distribution input
- USB connection to PC
- Microsoft Windows-based evaluation software with simple graphical user interface
- On-board PLL loop filter
- Easy access to digital I/O and diagnostic signals via I/O header
- Status LEDs for diagnostic signals
Application Notes (11)
Software & Systems Requirements
Tools & Simulations
AD9517-x IBIS Models
ADIsimCLK is the design tool developed specifically for Analog Devices' range of ultra-low jitter clock distribution and clock generation products. Whether your application is in wireless infrastructure, instrumentation, networking, broadband, ATE or other areas demanding predictable clock performance, ADIsimCLK will enable you to rapidly develop, evaluate and optimize your design.
Product Selection Guide (1)
Technical Articles (6)
Rarely Asked Questions (12)
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.
Sample & Buy
The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.