-
AD9516-2 Bill of Materials (Rev. D)12/10/2009
-
AD9516 Simulation File for the ADIsimCLK (clk, 62.4 KB)7/27/2007
-
AD9516 Gerber Files (Rev. D)7/27/2007
Overview
Features and Benefits
- Low phase noise, phase-locked loop (PLL)
On-chip VCO tunes from 2.05 GHz to 2.33 GHz
External VCO/VCXO to 2.4 GHz optional
1 differential or 2 single-ended reference inputs - 6 pairs of 1.6 GHz LVPECL outputs
Each output pair shares a 1-to-32 divider with coarse phase delay
Additive output jitter: 225 fs rms
Channel-to-channel skew paired outputs of <10 ps
- 4 pairs of 800 MHz LVDS clock outputs
Each output pair shares two cascaded 1-to-32 dividers with coarse phase delay
Additive output jitter: 275 fs rms
Automatic synchronization of all outputs on power-up
Manual output synchronization available
64-lead LFCSP - See datasheet for additional features
Product Details
The AD9516-2 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 2.05 GHz to 2.33 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz can be used.
The AD9516-2 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements.
The AD9516-2 features six LVPECL outputs (in three pairs) and four LVDS outputs (in two pairs). Each LVDS output can be reconfigured as two CMOS outputs. The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz.
Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow a range of divisions up to a maximum of 1024.
The AD9516-0 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5 V. A separate LVPECL power supply can be from 2.5 V to 3.3 V (nominal).
The AD9516-2 is specified for operation over the standard industrial range of −40°C to +85°C.
APPLICATIONS
- Low jitter, low phase noise clock distribution
- 10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4
- Forward error correction (G.710)
- Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
- High performance wireless transceivers
- ATE and high performance instrumentation
Product Categories
Markets and Technologies
Product Lifecycle
Recommended for New Designs
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
Evaluation Kits (1)
Documentation & Resources
-
AN-835: Understanding High Speed ADC Testing and Evaluation (Rev. B)5/12/2015
-
AN-501: Aperture Uncertainty and ADC System Performance (Rev. A)2/14/2015
-
AN-0983: Introduction to Zero-Delay Clock Timing Techniques (Rev. 0)2/14/2015
-
AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev. 0)2/14/2015
-
AN-769: Generating Multiple Clock Outputs from the AD9540 (Rev. 0)2/14/2015
-
AN-939: Super-Nyquist Operation of the AD9912 Yields a High RF Output Signal (Rev. 0)2/14/2015
-
AN-837: DDS-Based Clock Jitter Performance vs. DAC Reconstruction Filter Performance (Rev. 0)2/14/2015
-
AN-823: Direct Digital Synthesizers in Clocking Applications Time (Rev. 0)2/14/2015
-
AN-927: Determining if a Spur is Related to the DDS/DAC or to Some Other Source (For Example, Switching Supplies) (Rev. 0)2/14/2015
-
AN-0974: Multicarrier TD-SCMA Feasibility (Rev. 0)3/2/2010
-
AN-873: Lock Detect on the ADF4xxx Family of PLL Synthesizers (Rev. 0)12/6/2006
-
AN-741: Little Known Characteristics of Phase Noise (Rev. 0)11/29/2004
-
AD9516 Schematic (Rev. D)7/27/2007
-
FAQs7/26/2017
-
Low-power direct digital synthesizer cores enable high level of integration2/20/2008
-
Improved DDS Devices Enable Advanced Comm Systems9/1/2006
-
ADI Buys Korean Mobile TV Chip Maker6/7/2006
-
Design A Clock-Distribution Strategy With Confidence4/27/2006
-
Understand the Effects of Clock Jitter and Phase Noise on Sampled Systems12/7/2004
-
Speedy A/Ds Demand Stable Clocks3/22/2004
-
Resolution vs. ENOB – Still Hazy After All These Years2/1/2013
-
Considerations on High-Speed Converter PCB Design, Part 4: Plane Coupling2/1/2012
-
Crosstalkin’ Converters11/1/2011
-
Balancing Phase in High-Speed Converters8/1/2011
-
Considerations on High-Speed Converter PCB Design, Part 3: The E-Pad Low Down5/1/2011
-
Considerations on High-Speed Converter PCB Design, Part 2: Power and Ground Planes.2/1/2011
-
Considerations on High-Speed Converter PCB Design, Part 1: Power and Ground Planes.11/1/2010
-
Watch for Those Multiple Clocking Edges!8/1/2010
-
Taming A/D Converter Power Supplies3/1/2010
-
What’s the (Converter) Frequency Kenneth?9/1/2009
-
Keeping Common Modes Common4/1/2009
-
Are Your Filters Filtering?2/1/2009
Tools & Simulations
Design Tools
ADIsimCLK is the design tool developed specifically for Analog Devices' range of ultra-low jitter clock distribution and clock generation products. Whether your application is in wireless infrastructure, instrumentation, networking, broadband, ATE or other areas demanding predictable clock performance, ADIsimCLK will enable you to rapidly develop, evaluate and optimize your design.
Reference Designs (1)
Product Recommendations
AD9516-2 Companion Parts
Design Resources
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.View our quality and reliability program and certifications for more information.
Part Number | Material Declaration | Reliability Data | Pin/Package Drawing | CAD Symbols, Footprints & 3D Models |
---|---|---|---|---|
AD9516-2BCPZ | Material Declaration | Reliability Data | 64-Lead LFCSP (9mm x 9mm w/ EP) | |
AD9516-2BCPZ-REEL7 | Material Declaration | Reliability Data | 64-Lead LFCSP (9mm x 9mm w/ EP) | |
Wafer Fabrication Data |
PCN-PDN Information
Select a model from the dropdown below to subscribe to PCN/PDN notifications and view past notifications as well.
Support & Discussions
Sample & Buy
Ordering FAQs
See our Ordering FAQs for answers to questions about online orders, payment options and more.
Buy Now Pricing
(**) Displayed Buy Now Price and Price Range is based on small quantity orders.
List Pricing
(*)The 1Ku list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.
Lead Times
Please see the latest communication from our CCO regarding lead times.
Sampling
Selecting the Sample button above will redirect to the third-party ADI Sample Site. The part selected will carry over to your cart on this site once logged in. Please create a new account there if you have never used the site before. Contact SampleSupport@analog.com with any questions regarding this Sample Site.
Evaluation Boards
Pricing displayed is based on 1-piece.
Up to two boards can be purchased through Analog.com. To order more than two, please purchase through one of our listed distributors.
Pricing displayed is based on 1-piece. The USA list pricing shown is for budgetary use only, shown in United States dollars (FOB USA per unit), and is subject to change. International prices may vary due to local duties, taxes, fees and exchange rates.