AD9207
RECOMMENDED FOR NEW DESIGNS12-Bit, 6 GSPS, JESD204B/C Dual Analog-to-Digital Converter
- Part Models
- 2
- 1ku List Price
- Starting From $1217.25
Overview
- Buffered input with −3 dB bandwidth ≥ 7.5 GHz
- Full-scale of 1.4 V p-p with RIN = 100 Ω
- Overload protection clamp
- Supports dc-coupled with common-mode feedback
- AC performance at fIN < 2.6 GHz
- HD2 < −63 dBc and HD3 < −67 dBc
- Small signal (−12 dBFS) noise spectral density (NSD) = −153 dBFS/Hz
- Low code error rate (CER) < 2 × −10−15
- Flexible ADC clocking options
- On-chip PLL or external RF clock
- Versatile digital features
- Configurable digital down conversion (DDC)
- 2 coarse complex DDCs per ADC
- 4 fine complex DDCs per ADC
- Programmable 192 tap FIR filter
- Integer/fractional sample delay for digital predistortion (DPD) or IQ mismatch
- Power consumption~ 4 W to 5.5 W
- Automatic gain control (AGC) support with dedicated AGC support pins
- Fast detect with low latency for fast AGC control
- Signal monitor for slow AGC control
- Auxiliary features
- Fast frequency hopping
- ADC clock driver with selectable divide ratios
- On-chip temperature sensor
- Programmable GPIO pins
- JESD204B/C (Subclass 1) interface, 8 lanes
- JESD204B compatible with the maximum 15.5 Gbps lane rate
- JESD204C compatible with the maximum 24.75 Gbps lane rate
- Sample/bit repeat mode for receive lane rate matching
- Supports real or complex digital data (12-bit, 16-bit, or 24-bit)
- Multichip synchronization
- 15 mm × 15 mm BGA with 0.8 mm pitch
The AD9207 is a dual, 12-bit, 6 GSPS analog-to-digital converter (ADC). The ADC input features an on-chip wideband buffer with overload protection. This device is designed to support communications applications capable of direct sampling wideband signals up to 7.5 GHz. An optional low phase noise phase-locked loop (PLL) clock synthesizer is available to generate the ADC sampling clock, simplifying printed circuit board (PCB) distribution of a high frequency clock signal. Alternatively, the CLKIN of the device can be driven directly with the ADC sampling clock (or a higher version up to 12 GHz when the internal clock divider is enabled). An optional CLKOUT buffer is available to transmit the ADC sampling clock to other devices.
APPLICATIONS
- Diversity multiband and multimode digital receivers
- Microwave point-to-point, E-Band, and 5G mm wave
- Broadband communications systems
- Phased array radar and electronic warfare
- Electronic test and measurement systems
Documentation
Data Sheet 1
User Guide 1
Application Note 1
Design Note 1
Technical Articles 5
FPGA Interoperability Reports 1
Device Drivers 1
Analog Dialogue 1
Video Series 1
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal. View our quality and reliability program and certifications for more information.
| Part Model | Pin/Package Drawing | Documentation | CAD Symbols, Footprints, and 3D Models |
|---|---|---|---|
| AD9207BBPZ-6G | 324-Ball BGA_ED (15mm x 15mm x 1.58mm) | ||
| AD9207BBPZRL-6G | 324-Ball BGA_ED (15mm x 15mm x 1.58mm) |
This is the most up-to-date revision of the Data Sheet.
Software Resources
Device Drivers 2
- AD908x GitHub Linux Driver Source Code
API Device Drivers 1
Device Application Programming Interface (API) C code drivers provided as reference code that allows the user to quickly configure the product using high-level function calls. The library acts as an abstraction layer between the application and the hardware. The API is developed in C99 to ensure agnostic processor and operating system integration. Customers can port this application layer code to their embedded systems by integrating their platform-specific code base to the API HAL layer.
To request this software package, go to the Software Request Form signed in with your MyAnalog account and under “Target Hardware” select “High Speed Data Converters” and choose the desired API product package.
Evaluation Software 1
JESD204x Frame Mapping Table Generator
The JESD204x Frame Mapping Table Generator tool consists of two Windows executables that will allow the user to input any valid combination of JESD204x parameters (L, M, F, S, NP) in order to output a .csv file that illustrates the frame mapping of the JESD204x mode in table format. There is an executable that allows the user to input a single JESD204x mode and another, that allows the user to input the parameters for multiple JESD204x modes in a specified .csv format in order to output a .csv file that illustrates the frame mapping of each of the JESD204x modes that were input into separate tables.
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Hardware Ecosystem
| Parts | Product Life Cycle | Description |
|---|---|---|
| Clock ICs 4 | ||
| HMC7043 | RECOMMENDED FOR NEW DESIGNS |
High Performance, 3.2 GHz, 14-Output Fanout Buffer with JESD204B/JESD204C |
| LTC6953 | LAST TIME BUY | Ultralow Jitter, 4.5GHz Clock Distributor with 11 Outputs and JESD204B/JESD204C Support |
| LTC6952 | LAST TIME BUY | Ultralow Jitter, 4.5GHz PLL with 11 Outputs and JESD204B / JESD204C Support |
| HMC7044 | RECOMMENDED FOR NEW DESIGNS | High Performance, 3.2 GHz, 14-Output Jitter Attenuator with JESD204B and JESD204C Support |
| Differential Amplifiers 2 | ||
| ADL5569 | RECOMMENDED FOR NEW DESIGNS | 6.5 GHz, Ultrahigh Dynamic Range, Differential Amplifier |
| ADL5580 | RECOMMENDED FOR NEW DESIGNS | Fully Differential, 10 GHz ADC Driver with 10 dB Gain |
| Fanout Buffers 1 | ||
| LTC6955 | LAST TIME BUY | Ultralow Jitter, 7.5GHz, 11 Output Fanout Buffer Family |
| LDO Linear Regulators 4 | ||
| ADP1765 | RECOMMENDED FOR NEW DESIGNS | 5 A, Low VIN, Low Noise, CMOS Linear Regulator |
| ADP7158 | RECOMMENDED FOR NEW DESIGNS | 2 A, Ultralow Noise, High PSRR, Fixed Output, RF Linear Regulator |
| ADM7172 | RECOMMENDED FOR NEW DESIGNS | 6.5 V, 2 A, Ultralow Noise, High PSRR, Fast Transient Response CMOS LDO |
| ADM7150 | RECOMMENDED FOR NEW DESIGNS | 800 mA, Ultra Low Noise/High PSRR LDO |
| Phase-Locked Loop (PLL) Synthesizers 1 | ||
| ADF4377 | RECOMMENDED FOR NEW DESIGNS | Microwave Wideband Synthesizer with Integrated VCO |
| Switching Regulators & Controllers 5 | ||
| LTM4633 | RECOMMENDED FOR NEW DESIGNS | Triple 10A Step-Down DC/DC μModule (Power Module) Regulator |
| LTM8053 | RECOMMENDED FOR NEW DESIGNS | 40VIN, 3.5A/6A Step-Down Silent Switcher μModule Regulator |
| LTM8063 | RECOMMENDED FOR NEW DESIGNS | 40VIN, 2A Silent Switcher µModule Regulator |
|
LTM4644 LTM4644-1 |
Quad DC/DC μModule (Power Module) Regulator with Configurable 4A Output Array | |
| LTM4616 | RECOMMENDED FOR NEW DESIGNS | Dual 8A per Channel Low VIN DC/DC μModule (Power Module) Regulator |
Tools & Simulations
ADIsimPLL™
ADIsimPLL enables the rapid and reliable evaluation of new high performance PLL products from ADI. It is the most comprehensive PLL Synthesizer design and simulation tool available today. Simulations performed include all key non-linear effects that are significant in affecting PLL performance. ADIsimPLL removes at least one iteration from the design process, thereby speeding the design- to-market.
Open ToolMxFE JESD204 Mode Selector Tool
The JESD204B/C Mode Selector Tool is a simple command line-based Windows executable that can be used to narrow down the number of JESD204x modes to only include those modes that support the user’s specific application use case. The tool guides the user through a use case description flow chart and gives the user a small list of applicable transmit and/or receive modes to choose from. This tool is applicable to the AD9081, AD9082, AD9177, AD9207, AD9209, AD9986, and AD9988.
Open ToolADC Companion Transport Layer RTL Code Generator Tool
This command line executable tool generates a Verilog module which implements the JESD204 receive transport layer. The user specifies in a configuration file one or more modes to be supported by the transport layer module. These modes are defined as a set of JESD204 parameter values: L, M, F, S, N', and CF. The transport layer converts JESD204 lane data output from a JESD204 link layer IP to a data bus with a fixed width, containing interleaved virtual converter samples. Both JESD204B and JESD204C link layers are supported.
Open ToolHigh Speed Converter Toolbox for MATLAB
Open ToolAD9207/AD9209 AMI Model
Open ToolS-Parameter 2
Thermal Models 1
Evaluation Kits
AD9082 Evaluation Board
Resources
ADS9-V2EBZ Evaluation Board