14-Bit, 1 GSPS/820 MSPS/500 MSPS JESD204B, Dual Analog-to-Digital Converter
The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.
The analog input and clock signals are differential inputs. Each ADC data output is internally connected to two digital downconverters (DDCs). Each DDC consists of four cascaded signal processing stages: a 12-bit frequency translator (NCO), and four half-band decimation filters. The DDCs are bypassed by default.
In addition to the DDC blocks, the AD9680 has several functions that simplify the automatic gain control (AGC) function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.
Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, or four-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF± and SYNCINB± input pins.
The AD9680 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V to 3.3 V capable 3-wire SPI.
The AD9680 is available in a Pb-free, 64-lead LFCSP and is specified over the −40°C to +85°C industrial temperature range. This product is protected by a U.S. patent.
- Wide full power bandwidth supports IF sampling of signals up to 2 GHz.
- Buffered inputs with programmable input termination eases filter design and implementation.
- Four integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers.
- Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements.
- Programmable fast overrange detection.
- 9 mm × 9 mm, 64-lead LFCSP.
- Diversity multiband, multimode digital receivers
3G/4G, TD-SCDMA, W-CDMA, GSM, LTE
- General-purpose software radios
- Ultrawideband satellite receivers
- Signals intelligence (SIGINT)
- DOCSIS 3.0 CMTS upstream receive paths
- HFC digital reverse path receivers
Comparable Parts Click to see all in Parametric Search
This product has been released to the market. The data sheet contains all final specifications and operating conditions. For new designs, ADI recommends utilization of these products.
The AD9680-1000EBZ/AD9234-1000EBZ/AD9690-1000EBZ is an evaluation board for the AD9680-1000 14-Bit, 1000MSPS JESD204B, Dual Analog-to-Digital Converter/ AD9234-1000 14-BIT, 1000 MSPS JESD204B, Dual Analog to Digital Converter/ AD9690-1000 14-Bit, 500 MSPS, 1 GSPS JESD204B, Analog-to-Digital Converter. This reference design provides all of the support circuitry required to operate the ADC in its various modes and configurations. It is designed to interface directly with the ADS7-V1EBZ data capture card, allowing users to download captured data for analysis. The Visual Analog software package, which is used to interface with the device's hardware, allows users to download captured data for analysis with a user-friendly graphical interface. The SPI Controller software package is also compatible with this hardware, and allows the user to access the SPI programmable features of the AD9680/AD9234/AD9690. The user guide wiki provides documentation and instructions to configure the device for performance evaluation in the lab.
The AD9680/AD9234/AD9690 data sheet provides additional information related to device configuration and performance, and should be consulted when using the evaluation board. All documents and Visual Analog and SPI Controller are available at the High Speed ADC Evaluation Boards page. For additional information or questions, please email firstname.lastname@example.org
- Analog signal source and antialiasing filter
- Sample Clock Source
- REFCLOCK source for FPGA receiver
- PC running Windows 7, XP or Vista
- USB 2.0 port recommended (USB 1.1 compatible)
- AD9680-1000EBZ Evaluation Board
- ADs7-v1EBZ FPGA Based Data Capture Board
- Electronic test and measurement equipment
- General-purpose software radios
- Radar systems
- Ultra wideband satellite receivers
- Point-to-point communication systems
Recommended Differential Driver Amplifiers
Recommended Power Products
Recommended Power Solutions
For selecting voltage regulator products, use ADIsimPower.
JESD204 Serial Interface
The JESD204 and the JESD204B revision data converter serial interface standard was created through the JEDEC...
SDR: Software Defined Revolution
Take the next step in Software Defined Radio.
MS-2660: Understanding Spurious-Free Dynamic Range in Wideband GSPS ADCs
MS-2735: Maximizing the Dynamic Range of Software-Defined Radio
MS-2677: JESD204B Subclasses - Part 2: Subclass 1 vs. Subclass 2 System...
MS-2672: JESD204B Subclasses - Part 1: An Introduction to JESD204B...
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.
Didn't find what you were looking for?
The USA list pricing shown is for BUDGETARY USE ONLY, shown in United States dollars (FOB USA per unit for the stated volume), and is subject to change. International prices may differ due to local duties, taxes, fees and exchange rates. For volume-specific price or delivery quotes, please contact your local Analog Devices, Inc. sales office or authorized distributor. Pricing displayed for Evaluation Boards and Kits is based on 1-piece pricing.