Balancing Phase in High-Speed Converters


Why is analog input phase balance so important to my high-speed converter design?

RAQ:  Issue 72


Analog input phase balance is critical throughout the signal chain, because without proper balance, second-harmonic and other even-order distortion will arise. Analog input phase imbalance typically results when component tolerances or symmetric PCB layout are ignored during the design process.

Phase imbalance occurs when the two differential analog input signals sampled by the A/D converter are not exactly 180° out of phase. In the simplest case, the signals can be thought of as two sine waves. As these two sine waves move apart from "perfect" phase, distortion results. The distortion increases as the system frequency increases, with even-order distortion degrading even quicker.

Passive imbalance, caused by using a transformer or balun to couple the signal to the converter's analog inputs, generally begins around 100 MHz to 150 MHz with standard ferrites. Using two transformers or baluns can reduce the coupling differences and improve the phase balance. Unfortunately, transformers are large and expensive, so using two increases the board space and system cost. The other solution is to use a better transformer.

Active imbalance, caused by using an amplifier to drive the converter's analog inputs, generally happens if component tolerances are not adequate. To minimize beta variation, resistors with 1% or better tolerance should be used for setting the gain. Mismatch will cause the voltages on the summing nodes to differ slightly, resulting in errors on the amplifier’s differential outputs and giving rise to second order distortion.

Layout imbalance is caused by asymmetrical traces throughout the signal chain, with a sloppy layout causing decreased system performance. Second-order distortion can arise from asymmetrical connection to the differential input pins of the converter. This may not manifest itself at low frequencies, but nonlinearities will usually show up at frequencies above 100 MHz, so don't throw away your hard work; guide the CAD engineer to keep the front-end design symmetrical and well balanced.

ADC imbalance is caused by a mismatch in phase. The converter can tolerate a certain degree (pun intended) of phase mismatch, but keeping it to 4° or less will yield the best performance. The converter has some inherent imbalance, but designers work hard to keep the IC well balanced internally.


Rob Reeder

Rob Reeder

Rob Reeder is a senior system application engineer with Analog Devices in the High Speed Converter and RF Applications Group in Greensboro, North Carolina. He has published numerous articles on converter interfaces, converter testing, and analog signal chain design for a variety of applications. Formerly, Rob was an application engineer for the Aerospace and Defense Group for five years, where he focused on a variety of radar, EW, and instrumentation applications. Previously he was part of the high speed converter product line for nine years. His prior experience also includes test development and analog design engineering for the Multichip Products Group at ADI, where he designed analog signal chain modules for space, military, and high reliability applications for five years. Rob received his M.S.E.E. and B.S.E.E. from Northern Illinois University in DeKalb, Illinois, in 1998 and 1996, respectively. When Rob isn’t writing papers late at night or in the lab hacking up circuits, he enjoys hanging around at the gym, listening to techno music, building furniture out of old pallets, and, most importantly, chilling out with his two boys.