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ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 SHARCプロセッサ (Rev. E)2/10/2010PDF4364 kB
最新情報 (1)
製品概要
機能と利点
- 333MHz /1.8 GFLOPs SIMD SHARC core supporting IEEE 32-bit floating-point, 40-bit floating-point and 32-bit fixed-point data types
- 25 zero-overhead DMA channels
- Digital Audio Interface (DAI) enabling user-definable access to peripherals including an S/PDIF Tx/Rx, 8-channel asynchronous sample rate converter, and Data Transmission Content Protection hardware accelerator
- 6 serial ports (SPORTs) supporting I2S, left-justified sample pair, and TDM modes
- 2 SPI-compatible ports supporting master and slave modes
- 16 Pulse Width Modulation (PWM) channels
- 3 full-featured timers
- 136-ball MBGA and 144-Ld LQFP E-Pad
package options - Commercial and Industrial temperature ranges
製品概要
The third generation of SHARC® Processors, which includes the ADSP-21261, ADSP-21262, ADSP-21266, ADSP-21267, ADSP-21363, ADSP-21364, ADSP-21365, and ADSP-21366, offers increased performance, audio and application-focused peripherals, and memory configurations capable of supporting surround-sound decoder algorithms. All devices are pin-compatible and completely code-compatible with all prior SHARC Processors. These members of the SHARC Processor family are based on a single-instruction, multiple-data (SIMD) core, which supports both 32-bit fixed-point and 32-/40-bit floating-point arithmetic formats making them particularly suitable for high-performance audio applications.
The ADSP-21362 offers the highest performance – 333 MHz/2 GFLOPs -- within the third generation SHARC Processor family. This level of performance makes the ADSP-21362 particularly well suited to address the increasing requirements of the professional and automotive audio market segments. In addition to its higher core performance, the ADSP-21362 includes additional value-added peripherals such as an S/PDIF transmitter/receiver, 8-channel asynchronous sample rate converter, and a hardware Digital Transmission Content Protection (DTCP) encryption/decryption block.
Third generation SHARC Processors also integrate application-specific peripherals designed to simplify hardware design, minimize design risks, and ultimately reduce time to market. Grouped together, and broadly named the Digital Audio Interface (DAI), these functional blocks may be connected to each other or to external pins via the software-programmable Signal Routing Unit (SRU). The SRU is an innovative architectural feature that enables complete and flexible routing amongst DAI blocks. Peripherals connected through the SRU include but are not limited to serial ports, SPI ports, S/PDIF Tx/Rx, DTCP Accelerator, and an 8-Channel asynchronous sample rate converter block.
製品ライフサイクル
製造中
この製品ファミリーの1つ以上の型番が生産／供給中です。新規の設計に適していますが、より新しい代替製品を提供している場合があります。
評価キット (3)
参考資料
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EE-112: Class Implementation in Analog C++11/14/2016PDF31 K
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EE-356: エミュレータ／評価ハードウェアのトラブルシューティング・ガイド CCES 対応版 (Rev. 1)10/4/2012PDF0
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• EE-356: Associated Files (Rev 1, 09/2012)
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EE-355: Expert In-Circuit FLASH Programmer for SHARC® Processors (Rev. 1)8/20/2012PDF1045 kB
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• EE-355: Code Example (Rev 1, 08/2012)
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EE-243: Using the Expert DAI for SHARC® Processors (Rev. 7)7/6/2010PDF337 kB
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• EE-243: Code example (Rev 7, 06/2010)
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EE-230: 第3世代SHARC&®;ファミリー・プロセッサでのコード・オーバーレイ (Rev. 2)2/3/2010PDF355 kB
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• EE-230 Software Code (4/2005)
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EE-345: Boot Kernel Customization and Firmware Upgradeability on SHARC Processors® (Rev. 1)10/6/2009PDF331 kB
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• EE-345: Code example (Rev 1, 10/2009)
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EE-332: Cycle Counting and Profiling (Rev. 2)8/18/2009PDF142 kB
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• EE-332: Code example
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EE-322: Expert Code Generator for SHARC® Processors (Rev. 5)6/15/2009PDF742 kB
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• EE-322: Code Example (Rev 5, 01/2012)
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EE-340: SPIによるSHARC®とBlackfin®間接続 (Rev. 1)7/11/2008PDF682 kB
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• EE-340: Code example (Rev 1, 07/2008)
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EE-320: Implementing an Ogg Vorbis Decoder on SHARC® Processors (Rev. 1)6/26/2008PDF731 kB
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• EE-320: Code example (Rev 1, 06/2008)
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EE-323: Implementing Dynamically Loaded Software Modules (Rev. 1)3/8/2008PDF0
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• EE-323: Associated Code
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EE-330: Windows Vista Compatibility in VisualDSP++ 5.0 Development Tools (Rev. 1)8/31/2007PDF276 kB
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EE-266: Programming S/PDIF on ADSP-2136x and ADSP-21371 SHARC® Processors (Rev. 2)8/28/2007PDF1147 kB
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• EE-266: Code example (Rev 2, 08/2007)
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EE-231: In-Circuit Programming of an SPI Flash with SHARC® Processors (Rev. 2)8/27/2007PDF74 kB
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• EE-231: Code example (Rev 2, 08/2007)
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EE-328: Migrating from ADSP-2106x/2116x to ADSP-2126x/2136x/2137x SHARC® Processors (Rev. 1)7/27/2007PDF101 kB
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EE-175: Emulator and Evaluation Hardware Troubleshooting Guide for VisualDSP++ Users (Rev. 14)5/21/2007PDF183 kB
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• EE-175: Associated Files
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EE-56: Tips and Tricks on SHARC® EPROM and Host Boot Loader (Rev. 3)3/7/2007PDF108 kB
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EE-84: External Port DMA Modes of Operation for SHARC Processors (Rev. 2)3/2/2007PDF99K
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• EE-84: Code Example (Rev 2, 2/2007)
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EE-223: In-Circuit Flash Programming on SHARC® Processors (Rev. 2)2/23/2007PDF258 kB
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• EE-223: Code Example (Rev 2, 02/2007)
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EE-253: Power Bypass Decoupling of SHARC® Processors (Rev. 1)12/5/2006PDF354 kB
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EE-296: Using the UART Port Controller on SHARC® Processors (Rev. 2)11/22/2006PDF114 kB
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EE-295: Implementing Delay Lines on SHARC® Processors (Rev. 1)11/15/2006PDF0 kB
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• EE-295: Code Example (Rev 1, 10/2006)
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EE-305: SHARC®プロセッサ採用システムのデザインとデバッグ (Rev. 1)11/15/2006PDF350 kB
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EE-290: Managing the Core PLL on SHARC® Processors (Rev. 5)7/12/2006PDF409 kB
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• EE-290: Code Example (Rev 5, 03/2012)
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EE-277: Estimating Power for the ADSP-21362 SHARC® Processors (Rev. 1)3/9/2006PDF130 kB
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EE-220: Using External Memory with Third Generation SHARC® Processors and the Parallel Port (Rev. 2)8/10/2005PDF80 kB
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EE-270: Extended-Precision Fixed-Point Arithmetic on SIMD SHARC® Processors (Rev. 1)7/8/2005PDF86 kB
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• EE-270 Software Code
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EE-264: Interfacing MultiMediaCard™ with ADSP-2126x SHARC® Processors (Rev. 1)5/6/2005PDF975 kB
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• EE-264 Software Code
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EE-268: Programming Asynchronous Sample Rate Converters on ADSP-2136x SHARC® Processors (Rev. 1)4/28/2005PDF2688 kB
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• EE-268 Software Code (04/2005)
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EE-267: Implementing In-Place FFTs on SISD and SIMD SHARC® Processors (Rev. 1)4/4/2005PDF32 kB
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• EE-267 Software Code
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EE-261: Understanding Jitter Requirements of PLL-Based Processors (Rev. 1)2/15/2005PDF90 kB
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EE-260: Interfacing AD7865 Parallel ADCs to ADSP-2136x SHARC® Processors (Rev. 1)12/17/2004PDF500 kB
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• EE-260 Software Code
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EE-254: Interfacing ADSP-21365 SHARC® PDAP to ADSP-BF533 Blackfin® EBIU (Rev. 1)11/18/2004PDF81 kB
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• EE-254 Software Code
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EE-248: Interfacing AD7676 ADCs to ADSP-21365 SHARC® Processors (Rev. 1)10/12/2004PDF307 kB
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• EE-248 Software Code
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EE-202: Using the Expert Linker for Multiprocessor LDFs (Rev. 3)9/15/2004PDF1186 kB
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• EE-202 Software Code
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EE-232: Configuring the Signal Routing Unit of ADSP-2126x SHARC® DSPs (Rev. 1)2/18/2004PDF70 kB
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EE-189: Link Port Tips & Tricks For ADSP-2106x & ADSP-2116x SHARC® DSPs10/27/2003PDF105 kB
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EE-191: Implementing a Glueless UART Using The SHARC® DSP SPORTs5/21/2003PDF174 kB
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• EE-191 Software Code
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EE-177: SHARC® SPI Slave Booting (Rev. 3)5/2/2003PDF43 kB
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• EE-177: Code Example (Rev 3, 01/2007)
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EE-68: Analog Devices JTAG Emulation Technical Reference (Rev. 10)12/20/2002PDF293 kB
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EE-128: DSP in C++: Calling Assembly Class Member Functions From C++9/18/2002PDF172 kB
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EE-69: Understanding and Using Linker Description Files on SHARC Processors (Rev. 2)9/17/2002PDF88 kB
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• EE-69: Code Example (Rev 2, 01/2007)
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EE-110: A Quick Primer on ELF and DWARF File Formats5/17/2000PDF19 kB
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EE-69: リンカー記述ファイルを使いこなす1/1/2000PDF
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• EE-69 Software Code
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EE-104: Setting Up Streams with the VisualDSP Debugger11/5/1999PDF120 kB
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• EE-104 Software Code
ZIP
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SHARC® Audio EZ-Extender® Manual (Rev. 1.1)11/11/2009PDF617 kB
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Blackfin®/SHARC® USB EZ-Extender® Manual (Rev. 1.1)5/7/2009PDF359 kB
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SHARC® EZ-Extender® Manual (Rev. 3.1)7/26/2006PDF235 kB
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SHARCプロセッサ：マニュアル5/17/2023
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Getting Started with SHARC2/14/2015
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SHARC® Processor Programming Reference (Includes ADSP-2136x, ADSP-2137x, and ADSP-214xx Processors) (Rev. 2.4)3/14/2007PDF5387 kB
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Documentation Errata
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ADSP-2136x SHARC® Processor Hardware Reference (includes the ADSP-21362/ADSP-21363/ADSP-21364/ADSP-21365/ADSP-21366 processors) (Rev. 2.1)11/15/2005PDF8397 kB
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VisualDSP++® 5.0 Assembler and Preprocessor Manual (Rev. 3.4)11/15/2009PDF3197 kB
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VisualDSP++® 5.0 C/C++ Compiler Manual for SHARC® Processors (Rev. 1.5)11/13/2009PDF2277 kB
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Documentation Errata
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VisualDSP++® 5.0 Loader and Utilities Manual (Rev. 2.5)11/13/2009PDF2246 kB
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Documentation Errata
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VisualDSP++® 5.0 Licensing Guide (Rev. 1.4)11/13/2009PDF392 kB
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VisualDSP++® 5.0 Kernel (VDK) Users Guide (Rev. 3.5)11/13/2009PDF2401 kB
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VisualDSP++® 5.0 Linker and Utilities Manual (Rev. 3.5)11/13/2009PDF2290 kB
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VisualDSP++® 5.0 Run-Time Library Manual for SHARC® Processors (Rev. 1.5)11/12/2009PDF2298 kB
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VisualDSP++® 5.0 Users Guide (Rev. 3.0)12/9/2007PDF2738 kB
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VisualDSP++® 5.0 Quick Installation Reference Card (Rev. 3.1)8/30/2007PDF91 kB
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VisualDSP++® 5.0 Getting Started Guide (Rev. 3.0)8/30/2007PDF2035 kB
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Documentation Errata
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VisualDSP++® 5.0 Product Release Bulletin (Rev. 3.0)8/30/2007PDF774 kB
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ICE-1000/ICE-2000 Emulator User’s Guide (Rev. 1.2)6/3/2014PDF321 kB
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HPUSB, USB, and HPPCI Emulator User’s Guide (Rev. 3.2)11/11/2009PDF746 kB
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ICE-100B Emulator User’s Guide (Rev. 1.1)11/11/2009PDF348 kB
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ADSP-21362 SHARC Anomaly List for Revisions 0.2, 0.4 (Rev. K)12/13/2006PDF162 K
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SHARCプロセッサ・ファミリー1/23/2011PDF1737 kB
ソフトウェア & システム
Software & Tools Anomalies
Code Examples
ADSP-2136x Application Code Examples - Single Channel
ADSP-2136x Application Code Examples - Multi Channel
Software Development Tools
CrossCore® Embedded Studio
CrossCore Embedded Studioは、アナログ・デバイセズのBlackfin®、SHARC®、Arm®の各プロセッサ・ファミリ向けに用意された、世界トップクラスの統合開発環境（IDE）です。
SigmaStudio®
アナログ・デバイセズのDSPオーディオ・プロセッサおよびA2B®（オートモーティブ・オーディオ・バス）トランシーバー向けにプログラミング、開発、チューニングを行うソフトウェアのグラフィック開発ツール
ツールおよびシミュレーション
設計ツール
SHARC プロセッサ ソフトウェア＆ツール
SHARC プロセッサ ソフトウェア＆ツールの一覧を掲載しております。
BSDL Model Files
Designing with BGA
Surface Mount Assembly Recommendations for Plastic Ball Grid Array (PBGA) Packages
