AD9252
warning : NOT RECOMMENDED FOR NEW DESIGNS
searchIcon
cartIcon

AD9252

Octal, 14-Bit, 50 MSPS, Serial LVDS, 1.8 V ADC

Show More showmore-icon

warning : NOT RECOMMENDED FOR NEW DESIGNS tooltip
warning : NOT RECOMMENDED FOR NEW DESIGNS tooltip
Part Details
Part Models 2
1ku List Price Starting From $72.28
Features
  • 8 analog-to-digital converters (ADCs) integrated into 1 package
  • 93.5 mW ADC power per channel at 50 MSPS
  • SNR = 73 dB (to Nyquist)
  • SFDR = 84 dBc (to Nyquist)
  • Excellent linearity
    - DNL = ±0.4 LSB (typical)
    - INL = ±1.5 LSB (typical)
  • Serial LVDS (ANSI-644, default)
    Low power, reduced signal option (similar to IEEE 1596.3)
  • Data and frame clock outputs
  • 325 MHz, full-power analog bandwidth
  • 2 V p-p input voltage range
  • 1.8 V supply operation
  • Please see the data sheet for additional information

Additional Details
show more Icon

The AD9252 is an octal, 14-bit, 50 MSPS ADC with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. Operating at a conversion rate of up to 50 MSPS, it is optimized for outstanding dynamic performance and low power in applications where a small package size is critical.

The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.

The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock (DCO) for capturing data on the output and a frame clock (FCO) for signaling a new output byte are provided. Individual channel power-down is supported and typically consumes less than 2 mW when all channels are disabled.

The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user- defined test patterns entered via the serial port interface (SPI).

The AD9252 is available in an RoHS compliant, 64-lead LFCSP. It is specified over the industrial temperature range of −40°C to +85°C.

Product Highlights

  1. Small Footprint. Eight ADCs are contained in a small package.
  2. Low Power of 93.5 mW per Channel at 50 MSPS.
  3. Ease of Use. A data clock output (DCO) operates up to 350 MHz and supports double data rate (DDR) operation.
  4. User Flexibility. SPI control offers a wide range of flexible features to meet specific system requirements.
  5. Pin-Compatible Family. This includes the AD9212 (10-bit) and AD9222 (12-bit).

Applications

  • Medical imaging and nondestructive ultrasound
  • Portable ultrasound and digital beam-forming systems
  • Quadrature radio receivers
  • Diversity radio receivers
  • Tape drives
  • Optical networking
  • Test equipment
Part Models 2
1ku List Price Starting From $72.28

close icon
Documentation

Documentation

Part Model Pin/Package Drawing Documentation CAD Symbols, Footprints, and 3D Models
AD9252ABCPZ-50
  • HTML
  • HTML
AD9252ABCPZRL7-50
  • HTML
  • HTML

Filter by Model

reset

Reset Filters

Part Models

Product Lifecycle

PCN

Feb 1, 2024

- 24_0009

Qualification of alternative Wafer Fab for TSMC 0.18um Mixed Signal CMOS Process

AD9252ABCPZ-50

PRODUCTION

AD9252ABCPZRL7-50

PRODUCTION

Filter by Model

reset

Reset Filters

Part Models

Product Lifecycle

PCN

Feb 1, 2024

- 24_0009

arrow down

Qualification of alternative Wafer Fab for TSMC 0.18um Mixed Signal CMOS Process

AD9252ABCPZ-50

PRODUCTION

AD9252ABCPZRL7-50

PRODUCTION

Software & Part Ecosystem

Software & Part Ecosystem

Can't find the software or driver you need?

Request a Driver/Software
Evaluation Kit

Evaluation Kits 2

EVAL-AD9252

AD9252 Evaluation Board

reference details image

HSC-ADC-EVALCZ

FPGA-Based Data Capture Kit

zoom

HSC-ADC-EVALCZ

FPGA-Based Data Capture Kit

FPGA-Based Data Capture Kit

Features and Benefits

  • 64kB FIFO Depth
  • Works with single and multi-channel ADCs
  • Use with VisualAnalog® software
  • Based on Virtex-4 FPGA
  • May require adaptor to interface with some ADC eval boards
  • Allows programming of SPI control Up to 644 MSPS SDR / 800MSPS DDR Encode Rates on each channel
  • DDR Encode Rates on each channel

Product Detail

The HSC-ADC-EVALCZ high speed converter evaluation platform uses an FPGA based buffer memory board to capture blocks of digital data from the Analog Devices high speed analog-to-digital converter (ADC) evaluation boards. The board is connected to the PC through a USB port and is used with VisualAnalog® to quickly evaluate the performance of high speed ADCs. The evaluation kit is easy to set up. Additional equipment needed includes an Analog Devices high speed ADC evaluation board, a signal source, and a clock source. Once the kit is connected and powered, the evaluation is enabled instantly on the PC.
Tools & Simulations

Tools & Simulations 4

Recently Viewed