The AD9250 is a dual, 14-bit ADC with sampling speeds of up to 250 MSPS. The AD9250 is designed to support communications applications where low cost, small size, wide bandwidth, and versatility are desired.
The ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. The ADC cores feature wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compensate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance. The JESD204B high speed serial interface reduces board routing requirements and lowers pin count requirements for the receiving device.
By default, the ADC output data is routed directly to the two JESD204B serial output lanes. These outputs are at CML voltage levels. Four modes support any combination of M = 1 or 2 (single or dual converters) and L = 1 or 2 (one or two lanes). For dual ADC mode, data can be sent through two lanes at the maximum sampling rate of 250 MSPS. However, if data is sent through one lane, a sampling rate of up to 125 MSPS is supported. Synchronization inputs (SYNCINB± and SYSREF±) are provided.
Flexible power-down options allow significant power savings, when desired. Programmable overrange level detection is supported for each channel via the dedicated fast detect pins.
Programming for setup and control are accomplished using a 3-wire SPI-compatible serial interface.
The AD9250 is available in a 48-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.
|Title||Content Type||File Type|
|AD9250: 14-Bit, 170 MSPS/250 MSPS, JESD204B, Dual Analog-to-Digital Converter Data Sheet (Rev B, 12/2013) (pdf, 1174 kB)||Data Sheets|
JESD204B Converter-to-FPGA Connectivity
Watch the AD9250 a dual, 14-bit, 250 MSPS, ADC with a JESD204B high speed serial interface connected to a Xilinx KC705 development system run the Analog Devices reference design, which includes the Xilinx LogiCORE™ IP JESD204 core.
|UG-493: Quick Start Guide for Testing the AD9250/AD6673 Analog-to-Digital Converters (ADCs) Evaluation Boards Using the HSC-ADC-EVALDZ FPGA-Based Capture Board (pdf, 650 kB)||User Guides|
|JESD204B FPGA Debug Software Accelerates High-speed Design (11 Oct 2013)||Press Releases||HTML|
|Xilinx and Analog Devices Achieve JEDEC JESD204B Interoperability (24 Sep 2013)||Press Releases||HTML|
|FPGA Mezzanine Card Rapid Prototyping Kit Simplifies JESD204B-Compatible A/D Converter-to-FPGA Connectivity (26 Feb 2013)||Press Releases||HTML|
|FPGA Mezzanine Card Simplifies JESD204B-Compatible Data Converter-to-FPGA Connectivity (13 Nov 2012)||Press Releases||HTML|
|Analog Devices Simplifies High-Speed Data Converter-to-FPGA Interconnect Design Environment (08 Oct 2012)||Press Releases||HTML|
|Glossary of EE Terms||Glossary||HTML|
|Title||Content Type||File Type|
|AD9250 JESD204B Tx IBIS-AMI Model||IBIS Models||HTML|
|ADI AD-FMCJESDADC1-EBZ Boards & Xilinx Reference Design (Wiki Site)||Device Drivers||HTML|
|AD9250 Evaluation Board, ADC-FMC Interposer & Xilinx KC705 Reference Design (Wiki Site)||FPGA HDL||HTML|
|AD-FMCJESDADC1-EBZ Rapid Development Board & Xilinx Reference Design||FPGA HDL||HTML|
Evaluation board for AD9250 14 bit 170Msps / 250Msps JESD204B ADC, compatible with Analog Devices’ HSC-ADC-EVALDZ high speed data capture card , Visual Analog ™ converter performance analysis software, and SPI controller configuration software.
FMC-based reference board for rapid prototyping with the AD9250, 14-bit, 170 MSPS/250 MSPS, JESD204B, Dual Analog-to-Digital Converter. Interfaces directly to many FPGA development platforms, including the Xilinx ML605, KC705 and VC707 platforms
Adapter board for interfacing AD9250 Evaluation Board to FMC-compatible platforms
Symbols and Footprints— Analog Devices offers Symbols & Footprints which are compatible with a large set of today’s CAD systems for broader and easier support.
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