CN0363

A clock set to a user-programmable frequency modulates one of the three LED colors with a constant current driver built around the AD8615 op amp, the ADG819 switch, and the AD5201 digital potentiometer. The beam splitter sends half the light through the sample container and half through the reference container. The ADA4528-1, configured as a transimpedance amplifier, then converts the photodiode current into an output voltage square wave, whose amplitude is proportional to the light transmitted through the sample or reference containers. The transimpedance amplifiers use the ADG633 single-pole, double-throw (SPDT) switches to select one of two transimpedance gains. The AD7175-2 Σ-Δ ADC samples the voltage and sends the digital data to an FPGA for digital demodulation.

The FPGA implements synchronous demodulation by first synchronizing a numerically generated sine wave with the LED clock, and then multiplying this sine wave with the sampled ADC data. In addition, a 90° shifted version of this sine wave is also multiplied with the ADC data to obtain the quadrature component of the modulation signal. The result of these operations are two low frequency demodulated signals representing the in-phase and quadrature components of the received light on each channel, respectively. A narrow FIR low pass filter removes all other frequency components, making it easy to calculate the magnitude and phase shift of the amplitude measured at the photodiodes, while rejecting any light or electrical noise at frequencies different from the LED clock. The ADG704 multiplexer connects the power rail to one of the three LED colors, allowing the user to select the test wavelength through a 2-bit address. The AD8615 and an NPN transistor make up a simple current source, with the LED current given by 

where:

V_{NON-INVERTING} is the voltage at the non-inverting input of the AD8615.
R_EMITTER is the value of the resistor connected to the emitter of Transistor Q3.

The ADG819 SPDT switch is connected to the set point voltage and to ground, and its control pin is connected to the reference clock. As the clock oscillates between high and low, the set point to the current source changes from 0 mA to the desired output current, thereby generating a square wave signal.

The AD5201 digital potentiometer acts as a programmable resistor divider from the 2.5 V reference, allowing 33 different current output settings for the LED current.

Both the sample and reference containers receive one-half of the LED light energy, and absorb different amounts of light depending on the type and concentration of material in each container. The photodiode on the opposite side of each container generates a small current proportional to the amount of light received.

The first stage of each receiver channel consists of an ADA4528-1 op amp configured as a transimpedance amplifier to convert the output current of the photodiode to a voltage. The ADA4528-1 is an auto-zero amplifier resulting in negligible offset, no 1/f noise, and very low broadband noise (5.9 nV/√Hz). Like all auto-zero amplifiers, there is a noise spike at the auto-zero frequency. For the ADA4528-1, the frequency is approximately 200 kHz, but the circuit signal bandwidth rolls off well before then.

The input bias current of the op amp multiplied by the feedback resistor value appears at the output as an offset voltage. The input offset of the op amp voltage appears at the output with a gain dependent on the feedback resistor and the shunt resistance of the photodiode. In addition, any op amp input voltage offset appears across the photodiode, causing the dark current of the photodiode to increase. The ADA4528-1 is therefore ideally suited for this application because of its low offset voltage (2.5 μV).

Figure 2 shows a typical transimpedance amplifier with a single feedback resistor and its ideal transfer function.

Because some solutions under test can have very strong absorption characteristics, it is sometimes necessary to use large feedback resistors to measure the very small currents generated by the photodiode, while at the same time being able to measure large currents corresponding to highly diluted solutions. To address this challenge, the photodiode amplifiers of Figure 1 include two different selectable gains. One gain is set at 33 kΩ, while the other is set at 1 MΩ. Using a single SPDT switch connected to the output of the op amp to switch feedback resistors results in transimpedance gain error due to the on resistance of the ADG633. To avoid this problem, Figure 3 shows a better configuration where the ADG633 switch inside the feedback loop selects the desired resistor, while a second switch connects the next stage of the system to the selected feedback loop. The voltage at the output of the amplifier is 

which represents a gain error. However, because one of the ADG633 devices is outside the feedback loop, the output impedance of this stage is the on resistance of the ADG633 (typically 52 Ω), rather than the very low output impedance associated with the output of an op amp in closed-loop operation. The error due to the leakage current of the ADG633 (5 pA typical) is negligible.

Even the best rail-to-rail output amplifiers like the ADA4528-1 cannot swing their output completely to the rails. In addition, the input offset voltage on the ADA4528-1, although very small, can be negative. Rather than including a negative power supply to guarantee that the amplifier never clips, and that it can drive to 0.0 V, an ADA4805-1 op amp provides a buffered 100 mV voltage to bias the anode of the photodiode and the ADA4528-1. The ADA4805-1 is ideally suited as a reference voltage buffer  because it maintains unity gain stability when driving large capacitive loads used for decoupling. A second ADA4805-1 is also used to buffer the output of the AD5201 digital potentiometer that sets the LED current.

The output voltage of the photodiode amplifier swings between 0.1 V and 5.0 V. For the 33 kΩ range, the 4.9 V output span corresponds to a full-scale photodiode current of 148.5 μA. For the 1 MΩ range, it corresponds to a full-scale photodiode current of 4.9 μA. When operating in the 1 MΩ gain setting, it is important to shield the photodiode from external light to prevent the amplifier from saturating. Although the synchronous detection scheme described in the following sections strongly attenuates any frequencies that are not synchronous with the LED clock, the detection scheme cannot function properly if the ADC is returning saturated data.

The gain setting for each channel is independently selectable through the FPGA board.

ADC Sampling Rate and Modulation Frequency Selection

The AD7175-2 ADC is configured with the sinc5+sinc1 filter with an output data rate of 250 kSPS to sample both channels with single-cycle settling. This configuration results in an effective sampling rate of 25 kSPS on each channel (data for each channel is output every 40 μs). Any frequencies above 12.5 kHz (such as the odd harmonics of the square wave modulation) alias back into the passband of the ADC; however, the synchronous demodulation stage rejects these frequencies as long as they do not fall right on top of the modulation frequency. To avoid aliases of the modulation waveform folding back into its fundamental, select a modulation frequency according to the following relationship:

where:

F_MODULATION is the modulation frequency.
F_SAMPLE is the ADC effective output data rate. n is an integer (corresponding to the harmonics of the modulation frequency).

For example, in this system, the effective output data rate is 25 kSPS; therefore, if a modulation frequency of approximately 1 kHz is desired, the frequency must be 1020 Hz (n = 12) or 943 Hz (n = 13) to avoid alias problems. Using this method to select a modulation frequency eliminates the need for sharp anti-aliasing filters on the front end.

Digital Synchronous Detection

Rather than implementing synchronous detection in the hardware (see the Circuit Note CN-0312), this circuit takes the time-sampled data and uses an FPGA to implement digital synchronous detection. Figure 4 shows a representation of the digital synchronous detection block implemented in the FPGA. The FPGA generates the ac excitation signal to drive the LEDs, and a numerically generated sine wave locks to this signal in a digital phase-locked loop. The input signal is multiplied with the digital sine wave and with a 90° shifted version, resulting in two low frequency demodulated signals proportional to the in-phase and quadrature components of the input signal at the modulation frequency. As shown in Figure 4, the magnitude is the root of the sum of the squares of these two components. For more information on this demodulation technique, see the Learn More section.

Power Supplies

The EVAL-CN0363-PMDZ board is powered from an external 6 V to 12 V dc supply. The analog portion of the circuit is supplied by AVDD = 5 V from an ADP7102 low dropout regulator. The digital portion of the circuit is supplied by IOVDD = 3.3 V developed from an ADP1720 low dropout regulator. Alternatively, IOVDD can be supplied from the PMOD connector, VCC, via a link option.

The 2.5 V reference voltage is supplied by the internal 2.5 V reference of the AD7175-2 ADC.

Circuit Performance Measurements

To verify the noise performance of the system, acquire data with all of the LEDs disabled. The synchronous detector still operates at the LED clock frequency, but no light synchronous to this clock is detected; therefore, it removes all dc and ac signals.

Table 1 shows the noise-free bit performance.