ADM7171

The ADMX1002 is an ultra-low distortion sinewave and high-resolution arbitrary waveform generator. This high-performance module demonstrates a proprietary digital pre-distortion algorithm that reduces signal distortion below levels that can be achieved with high-performance digital-to-analog converters (DAC) and amplifiers alone. Its differential output can be set to common-mode levels often required to test high-performance analog-to-digital converters (ADC), audio codecs, and other audio ICs and systems. With an easy-to-use SPI interface and small-form factor, the ADMX1002 can be easily embedded into test systems, or simply used on the bench for measurement and characterization.

APPLICATIONS

• High-end audio test
• Analog-to-digital converter characterization and test
• Sensor and transducer test
• Frequency response and network analysis
• ATE

The AD9546 Evaluation Board is a compact, easy-to-use platform for evaluating all features of the AD9546 multiple input, 10-Output, Dual Channel, Numeric Clock Synchronizer. The AD9546 supports existing and emerging International Telecommunications Union (ITU) standards for the delivery of frequency, phase, and time of day over service provider packet networks, including ITU-G.8262, ITU-T G.812, ITU-T G.813, ITU-T G.823, ITU-T G.824, ITU-T G.825, and ITU-T G.8273.2.

The 10 clock outputs of the AD9546 are synchronized to any one of up to four input references. The digital phase-locked loops (DPLLs) reduce timing jitter associated with the external references. The digitally controlled loop and holdover circuitry continuously generate a low jitter output signal, even when all reference inputs fail. The AD9546 system clock is provided by a 52 MHz crystal. Alternatively, an external clock signal may be provided at a SMA connector (relative components must be populated to enable this functionality).

Applications

• 5G timing transport high precision synchronization
• Global positioning system (GPS), PTP (IEEE 1588), and synchronous Ethernet (SyncE) jitter cleanup and synchronization
• Optical transport networks (OTN), synchronous digital hierarchy (SDH), and macro and small cell base stations
• Small base station clocking (baseband and radio)
• Stratum 2, Stratum 3e, and Stratum 3 holdover, jitter cleanup, and phase transient control
• JESD204B support for analog-to-digital converter (ADC) and digital-to-analog converter (DAC) clocking
• Carrier Ethernet

The AD-FREQCVT1-EBZ is an add on board for the FMCOMMS3/4/5 boards which contain the AD9361. While the complete chip level design package can be found on the ADI product pages, information on the card, how to use it, the design package that surrounds it, and the software which can make it work, can be found on the analog wiki site.

The purpose of the AD-FREQCVT1-EBZ is frequency up or down conversion to allow the AD9361 to operate down to 1MHz.

The ADM7170ACP-EVALZ/ADM717Q1CP-EVALZ/ ADM7172ACP-EVALZ is an evaluation board used to demonstrate the functionality of the ADM7170, ADM7171, and ADM7172 linear regulators.

Simple device measurements, such as line and load regulation, dropout, and ground current, can be demonstrated with just a single voltage source, a voltmeter, an ammeter, and load resistors.

The AD-PZSDR2400TDD-EB is a 2.4GHz TDD analog module designed to work with the AD9361, a high performance, highly integrated RF transceiver intended for use in RF applications, such as 3G and 4G base station and test equipment applications, and software defined radios. The AD-PZSDR2400TDD-EB is affectionately dubbed the first 'RF personality card'. It plugs into the ADRV1CRR-FMC carrier card. 35mm U.FL coaxial cables connect the card to the ADRV9361-Z7035 SDR SOM providing access to the transmit and receive inputs of the AD9361. Information on the card, how to use it, the design package that surrounds it, and the software which can make it work, can be found on the wiki page.

The purpose of the AD-PZSDR2400TDD-EB is to provide the user with a path to condition the transmit or receive signals of the AD9361. Selection of TX or RX path is achieved by the 200MHz to 2.7GHz SPDT switch HMC546 controlled by the FPGA and accompanying software. The transmit path consists of a 2.4GHz filter, half watt driver amplifier ADL5324 and 2 watt power amplifier HMC921. The receive path consists of the same 2.4GHz filter as well as a low loss LNA HMC669.