Features and Benefits
- SNR: 83 dB (85 dBFS) to 10 MHz input
- SFDR: 87 dBc to 10 MHz input
- Noise figure: 15 dB
- Input impedance: 1 kΩ
- Power: 600 mW
- 1.8 V analog supply operation
- 1.8 V to 3.3 V output supply
- Selectable bandwidth
2.5 MHz/5 MHz/10 MHz real
5 MHz/10 MHz/20 MHz complex
- Output data rate: 30 MSPS to 160 MSPS
- See data sheet for additional features
The AD9262 is a dual, 16-bit analog-to-digital converter (ADC) based on a continuous time sigma-delta (Σ-Δ) architecture that achieves -87 dB of dynamic range over a 10 MHz input bandwidth.
The integrated features and characteristics unique to the continuous time Σ-Δ architecture significantly simplify its use and minimize the need for external components.
The AD9262 has a resistive input impedance that significantly relaxes the requirements of the driver amplifier. In addition, a 32× oversampled fifth-order continuous time loop filter significantly attenuates out of band signals and aliases, reducing the need for external filters at the input.
An external clock input or the integrated integer-N PLL provides the 640 MHz internal clock needed for the oversampled continuous time Σ-Δ modulator. On-chip decimation filters and sample rate converters reduce the modulator data rate from 640 MSPS to a user-defined output data rate between 30 MSPS to 160 MSPS, enabling a more efficient and direct interface.
The AD9262 incorporates an integrated dc correction and quadrature estimation block that corrects for gain and phase mismatch between the two channels. This functional block proves invaluable in complex signal processing applications such as direct conversion receivers.
The digital output data is presented in offset binary, Gray code, or twos complement format. A data clock output (DCO) is provided to ensure proper timing with the receiving logic. The AD9262 has the added feature of interleaving Channel A and Channel B data onto one 16-bit bus, simplifying on-board routing.
The ADC is available in three different bandwidth options of 2.5 MHz, 5 MHz, and 10 MHz, and operates on a 1.8 V analog supply and a 1.8 V to 3.3 V digital supply, consuming 600 mW. The AD9262 is available in a 64-lead LFCSP and is specified over the industrial temperature range (−40°C to +85°C).
- Continuous time Σ-Δ architecture efficiently achieves high dynamic range and wide bandwidth.
- Passive input structure reduces or eliminates the requirements for a driver amplifier.
- An oversampling ratio of 32× and high order loop filter provide excellent alias rejection reducing or eliminating the need for antialiasing filters.
- An integrated decimation filter, sample rate converter, PLL clock multiplier, and voltage reference provide ease of use.
- Integrated dc correction and quadrature error correction.
- Operates from a single 1.8 V analog power supply and 1.8 V to 3.3 V output supply.
- Baseband quadrature receivers: CDMA2000, WCDMA, multicarrier GSM/EDGE, 802.16x, and LTE
- Quadrature sampling instrumentation
- Medical equipment
- Radio detection and ranging (RADAR)
Product Lifecycle Not Recommended for New Designs
This designates products ADI does not recommend broadly for new designs.
Evaluation Kits (1)
The AD9262 evaluation board serves two purposes: as an evaluation platform for the 16-bit dual continuous time sigma delta ADC and as a direct conversion demonstration platform.
The AD9262 is a dual, 16-bit analog-to-digital converter (ADC) based on a continuous time sigma-delta (Σ-Δ) architecture that achieves 86 dB of dynamic range over a 10 MHz real or 20 MHz complex bandwidth. The integrated features and characteristics unique to the continuous time Σ-Δ architecture significantly simplify its use and minimize the need for external components. This evaluation board supports the AD9262 family of products, including the AD9262BCPZ-10, AD9262BCPZ-5, and AD9262BCPZ.
Documentation & Resources
AN-905: VisualAnalog™ Converter Evaluation Tool Version 1.0 User Manual8/18/2020
AN-878: High Speed ADC SPI Control Software (Rev. A)3/20/2018
AN-835: Understanding High Speed ADC Testing and Evaluation (Rev. B)5/12/2015
AN-282: Fundamentals of Sampled Data Systems2/14/2015
Interfacing the ADL5382 Quadrature I/Q Demodulator to the AD9262 16-Bit Continuous Time Sigma-Delta ADC as an RF-to-Bits Solution (Rev. AN-1236)5/8/2013
AN-1142: Techniques for High Speed ADC PCB Layout (Rev. 0)2/2/2012
AN-807: Multicarrier WCDMA Feasibility (Rev. 0)11/9/2007
AN-808: Multicarrier CDMA2000 Feasibility (Rev. 0)11/9/2007
AN-812: MicroController-Based Serial Port Interface (SPI) Boot Circuit (Rev. 0)9/20/2006
AN-283: Sigma-Delta ADCs and DACs9/24/2002
AD9262: Dual Continuous Time Sigma-Delta ADC11/28/2018
Tools & Simulations
AD9262 IBIS Model
ADIsimRF is an easy-to-use RF signal chain calculator. Cascaded gain, noise, distortion and power consumption can be calculated, plotted and exported for signal chains with up to 50 stages. ADIsimRF also includes an extensive data base of device models for ADI’s RF and mixed signal components.
AD9262 Companion Parts
Recommended Driver Amplifiers
Recommended Clock Drivers
Recommended External Reference
- For an accuarte, stable,.5V reference: ADR130.
ADI has always placed the highest emphasis on delivering products that meet the maximum levels of quality and reliability. We achieve this by incorporating quality and reliability checks in every scope of product and process design, and in the manufacturing process as well. "Zero defects" for shipped products is always our goal.
Sample & Buy
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