5G mmWave Wireless Communications

The ADMV1128 is a silicon on isolator (SOI), microwave, upconverter and downconverter optimized for 5G radio designs operating in the 24 GHz to 29.5 GHz frequency range.

Both upconverters and downconverters offer two modes of frequency translation. One mode is conversion from and/or to single-ended or complex intermediate frequency (IF) signals, which then pass through an on-chip 90° IF hybrid, known as IF mode.

The other mode is a direct conversion from and/or to differential baseband inphase/quadrature (I/Q) inputs and outputs, known as baseband mode. The I/Q baseband output common-mode voltage is programmable between 0 V and 1.5 V. The SPI provides fine adjustment of the quadrature phase to optimize I/Q demodulation performance.

When the device is used as an image rejecting downconverter, the unwanted image term is typically rejected to 24 dBc, before calibration. The ADMV1128 offers a square law power detector to allow monitoring of the power levels at the mixer inputs of the downconverter.

The RF receive input, RF transmit output, and local oscillator (LO) interface are all single-ended and matched to 50 Ω. The on-chip RF switch provides the option to combine the transmit and receive RF ports together for time division duplex (TDD) applications.

The serial port interface (SPI) provides adjustment of the quadrature phase to allow optimum sideband rejection. In addition, the SPI allows powering down the output envelope detector to reduce power consumption when carrier feedthrough optimization is not necessary.

The ADMV1128 upconverter and downconverter is housed in a compact, thermally enhanced, 6 mm × 6.5 mm, ball grid array (BGA) package. This BGA package enables the ability to heat sink the ADMV1128 from the top of the package for the most efficient thermal heat sinking. The ADMV1128 operates over the −40°C to +95°C T_C range.

APPLICATIONS

• Millimeter-wave 5G applications
• Point to point microwave radios
• Radar and electronic warfare systems
• Instrumentation and automatic test equipment (ATE)

The ADMV1139 is an silicon on isolator (SOI), microwave, upconverter and downconverter optimized for 5G radio designs operating in the 37 GHz to 48.2 GHz frequency range.

Both upconverters and downconverters offer two modes of frequency translation. One mode is conversion from and/or to complex intermediate frequency (IF) signals, which then pass through an on-chip 90° IF hybrid, known as IF mode.

The other mode is a direct conversion from and/or to single-ended or differential baseband inphase/quadrature (I/Q) inputs and outputs, known as baseband mode. The I/Q baseband output common-mode voltage is programmable between 0 V and 1.5 V. The SPI provides fine adjustment of the quadrature phase to optimize I/Q demodulation performance.

When the device is used as an image rejecting downconverter, the unwanted image term is typically rejected to 26 dBc, before calibration. The ADMV1139 offers a square law power detector to allow monitoring of the power levels at the mixer inputs of the downconverter.

The RF receive input, RF transmit output, and local oscillator (LO) interface are all single-ended and matched to 50 Ω. The on-chip RF switch provides the option to combine the transmit and receive RF ports together for time division duplex (TDD) applications.

The serial port interface (SPI) provides adjustment of the quadrature phase to allow optimum sideband rejection. In addition, the SPI allows powering down the output envelope detector to reduce power consumption when carrier feedthrough optimization is not necessary.

The ADMV1139 upconverter and downconverter is housed in a compact, thermally enhanced, 6 mm × 6.5 mm, ball grid array (BGA) package. This BGA package enables the ability to heat sink the ADMV1139 from the top of the package for the most efficient thermal heat sinking. The ADMV1139 operates over the −40°C to +95°C T_C range.

APPLICATIONS

The ADMV4828 is a silicon on insulator (SOI), 24.0 GHz to 29.5 GHz, mmW 5G beamformer. The RF integrated circuit (RFIC) is highly integrated and contains 16 independent transmit and receive channels. The ADMV4828 supports eight horizontal and eight vertical polarized antennas via independent RFV and RFH input/outputs.

In transmit mode, both the RFV input and RFH input signals feed into separate amplifiers. Each path after the amplifiers splits into eight independent channels via the 1:8 power splitters. In receive mode, input signals pass through either the vertical or horizontal receive channels and combine via two independent 8:1 combiners to the common RFV pin or RFH pin. In either mode, each transmit and receive channel includes a vector modulator (VM) to control the phase, and two digital variable gain amplifiers (DVGAs) to control the amplitude. The VM provides a full 360° phase adjustment range in either transmit or receive mode to provide 6 bits of resolution for 5.625° phase steps. A phase step policy for the transmit and receive VM is provided to ensure optimum phase step performance. The total DVGA dynamic range in transmit mode is 34.5, which provides 6 bits of resolution that results in 0.5 dB amplitude steps and 5 bits of resolution that results in 1 dB amplitude steps. In receive mode, the total dynamic range is 28 dB, which provides 5 bits of resolution that results in 0.5 dB amplitude steps and 5 bits of resolution that results in 1 dB amplitude steps. The DVGAs provide a flat phase response across the full gain range. A gain policy for DVGA1 and DVGA2 is provided in the AN-2074 Application Note, ADMV4828 Application Note to ensure optimized performance across the attenuation range with 0.5 dB step resolution from 0 dB to 34.5 dB attenuation for transmit mode and 0.5 dB step resolution from 0 dB to 28 dB attenuation for receive mode. The transmit channels contain individual transmit power detectors to detect either modulated or continuous wave signals to calibrate for each channel gain as well as channel to channel gain mismatch. Each receive channel contains an RF power overload circuit (receive channel overload detection circuit) to prevent potential damage to the device as a result of blocker instances. The ADMV4828 RF ports can be connected directly to a patch antenna to create a dual polarization mmW 5G subarray.

The ADMV4828 can be programmed using a 3-wire or 4-wire serial port interface (SPI). An integrated, on-chip low dropout (LDO) voltage regulator generates the 1.0 V supply for the SPI circuitry to reduce the number of supply domains required. Various SPI modes are available to enable fast startup and control during normal operation. The amplitude and phase for each channel can be set individually or multiple channels can be programmed simultaneously using the on-chip memory for beamforming. The on-chip memory can store up to 2048 beam positions that can be allocated for either transmit mode or receive mode for the horizontal channels and vertical channels. On-chip nonvolatile memory (NVM) is used to store the calibrated gain and phase offset coefficients and the reference values for each individual channel from the factory. These values are used to perform channel to channel or chip to chip calibration. In addition, four address pins (CHIP_ADDx) allow independent SPI control of up to 16 devices on the same serial lines. To control multiple devices via the same serial lines with the same instructions, activate broadcast mode via the external enable pin (BR_EN). Dedicated horizontal and vertical polarization load pins (LOAD_V and LOAD_H) provide the synchronization of all devices in the same array. A horizontal and vertical polarization transmit mode and receive mode control pin (TRX_H or TRX_V) is provided for fast switching between transmit mode and receive mode.

The ADMV4828 comes in a compact, 304-ball, 10 mm × 8.5 mm chip scale package ball grid array (CSP_BGA). The ADMV4828 operates over the −40°C to +95°C case temperature (T_C) range. This CSP_BGA package enables the ability to heatsink the ADMV4828 from the topside of the package for the most efficient thermal heatsinking and to allow flexible antenna placement on the opposite side of the printed circuit board (PCB).

APPLICATIONS

The ADMV4928 is a silicon on insulator (SOI), 37.0 GHz to 43.5 GHz, mmW 5G beamformer. The RF integrated circuit (RFIC) is highly integrated and contains 16 independent transmit and receive channels. The ADMV4928 supports eight horizontal and eight vertical polarized antennas via independent RFV and RFH input/outputs.

In transmit mode, both the RFV input and RFH input signals feed into separate amplifiers. Each path after the amplifiers splits into eight independent channels via the 1:8 power splitters. In receive mode, input signals pass through either the vertical or horizontal receive channels and combine via two independent 8:1 combiners to the common RFV pin or RFH pin. In either mode, each transmit and receive channel includes a vector modulator (VM) to control the phase, and two digital variable gain amplifiers (DVGAs) to control the amplitude. The VM provides a full 360° phase adjustment range in either transmit or receive mode to provide 6 bits of resolution for 5.625° phase steps. A phase step policy for the transmit and receive VM is provided to ensure optimum phase step performance. The total DVGA dynamic range in transmit mode is 34.5, which provides 6 bits of resolution that results in 0.5 dB amplitude steps and 5 bits of resolution that results in 1 dB amplitude steps. In receive mode, the total dynamic range is 28 dB, which provides 5 bits of resolution that results in 0.5 dB amplitude steps and 5 bits of resolution that results in 1 dB amplitude steps. The DVGAs provide a flat phase response across the full gain range. A gain policy for DVGA1 and DVGA2 is provided in the AN-2074 Application Note, ADMV4928 Application Note to ensure optimized performance across the attenuation range with 0.5 dB step resolution from 0 dB to 34.5 dB attenuation for transmit mode and 0.5 dB step resolution from 0 dB to 28 dB attenuation for receive mode. The transmit channels contain individual transmit power detectors to detect either modulated or continuous wave signals to calibrate for each channel gain as well as channel to channel gain mismatch. Each receive channel contains an RF power overload circuit (receive channel overload detection circuit) to prevent potential damage to the device as a result of blocker instances. The ADMV4928 RF ports can be connected directly to a patch antenna to create a dual polarization mmW 5G subarray.

The ADMV4928 can be programmed using a 3-wire or 4-wire serial port interface (SPI). An integrated, on-chip low dropout (LDO) voltage regulator generates the 1.0 V supply for the SPI circuitry to reduce the number of supply domains required. Various SPI modes are available to enable fast startup and control during normal operation. The amplitude and phase for each channel can be set individually or multiple channels can be programmed simultaneously using the on-chip memory for beamforming. The on-chip memory can store up to 2048 beam positions that can be allocated for either transmit mode or receive mode for the horizontal channels and vertical channels. On-chip nonvolatile memory (NVM) is used to store the calibrated gain and phase offset coefficients and the reference values for each individual channel from the factory. These values are used to perform channel to channel or chip to chip calibration. In addition, four address pins (CHIP_ADDx) allow independent SPI control of up to 16 devices on the same serial lines. To control multiple devices via the same serial lines with the same instructions, activate broadcast mode via the external enable pin (BR_EN). Dedicated horizontal and vertical polarization load pins (LOAD_V and LOAD_H) provide the synchronization of all devices in the same array. A horizontal and vertical polarization transmit mode and receive mode control pin (TRX_H or TRX_V) is provided for fast switching between transmit mode and receive mode.

The ADMV4928 comes in a compact, 239-ball, 10 mm × 7 mm chip scale package ball grid array (CSP_BGA). The ADMV4928 operates over the −40°C to +95°C case temperature (T_C) range. This CSP_BGA package enables the ability to heatsink the ADMV4928 from the topside of the package for the most efficient thermal heatsinking and to allow flexible antenna placement on the opposite side of the printed circuit board (PCB).

APPLICATIONS

The ADMV1228 is a 24.0 GHz to 29.5 GHz, mmW 5G dual channel upconverter, dual channel downconverter and beamformer integrated on a single chip. The RF integrated circuit (RFIC) combines two transmit/receive streams (2T2R) with 16 independent TX and RX beamformer channels in a 2 by 8 configuration supporting both single and dual polarization array designs.

The on-chip transmit receive switches connect the upconverter RF output and downconverter RF input for each polarization into eight independent channels via the 1:8 power splitters/combiners.

The ADMV1228 comes in a compact, chip scale ball grid array package. The ADMV1228 operates over the −40°C to +95°C case temperature (T_C) range. This package allows heatsinking the ADMV1228 from the topside of the package for the most efficient thermal heatsinking and to allow flexible antenna placement on the opposite side of the printed circuit board (PCB).

APPLICATIONS

The ADMV1239 is a 37.0 GHz to 43.5 GHz, mmW 5G dual channel upconverter, dual channel downconverter and beamformer integrated on a single chip. The RF integrated circuit (RFIC) combines two transmit/receive streams (2T2R) with 16 independent TX and RX beamformer channels in a 2 by 8 configuration supporting both single and dual polarization array designs.

The on-chip transmit receive switches connect the upconverter RF output and downconverter RF input for each polarization into eight independent channels via the 1:8 power splitters/combiners.

The ADMV1239 comes in a compact chip scale ball grid array package. The ADMV1239 operates over the −40°C to +95°C case temperature (T_C) range. This package allows heatsinking the ADMV1239 from the topside of the package for the most efficient thermal heatsinking and to allow flexible antenna placement on the opposite side of the printed circuit board (PCB).

APPLICATIONS