DS21Q48

5V、E1/T1/J1线路接口

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产品详情

Complete E1, T1, or J1 line interface unit (LIU)
Supports both long- and short-haul trunks
Internal software-selectable receive-side termination for 75Ω/100Ω/120Ω
5V power supply
32-bit or 128-bit crystal-less jitter attenuator requires only a 2.048MHz master clock for both E1 and T1 with option to use 1.544MHz for T1
Generates the appropriate line build outs, with and without return loss, for E1 and DSX-1 and CSU line build outs for T1
AMI, HDB3, and B8ZS, encoding/decoding
16.384MHz, 8.192MHz, 4.096MHz, or 2.048MHz clock output synthesized to recovered clock
Programmable monitor mode for receiver
Loopbacks and PRBS pattern generation/ detection with output for received errors
Generates/detects in-band loop codes, 1 to 16 bits including CSU loop codes
8-bit parallel or serial interface with optional hardware mode
Multiplexed and nonmultiplexed parallel bus supports Intel or Motorola
Detects/generates blue (AIS) alarms
NRZ/bipolar interface for TX/RX data I/O
Transmit open-circuit detection
Receive Carrier Loss (RCL) indication (G.775)
High-Z State for TTIP and TRING
50mA (rms) current limiter

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