概览
优势和特点
- 信噪比(SNR):71.8 dBc(72.8 dBFS,至70 MHz、125 MSPS)
- 无杂散动态范围(SFDR):85 dBc (至70 MHz、125 MSPS)
- 低功耗:750 mW (125 MSPS)
- 信噪比(SNR):71.6 dBc(72.6 dBFS,至70 MHz、150 MSPS)
- 无杂散动态范围(SFDR):84 dBc (至70 MHz、150 MSPS)
- 低功耗:820 mW (150 MSPS)
- 1.8 V模拟电源供电
- 1.8 V至3.3V CMOS输出电源或1.8 V LVDS输出电源
- 1至8整数输入时钟除法器
- 中频采样频率达450 MHz
- ADC内部基准电压源
- 集成ADC采样保持输入
- 灵活的模拟输入范围:1 V p-p至2 V p-p
- 欲了解更多特性,请参考数据手册
产品详情
The AD9640 is a dual 14-bit, 80/105/125/150 MSPS analog-to-digital converter (ADC). The AD9640 is designed to support communications applications where low cost, small size, and versatility are desired.The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compen-sate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.
The AD9640 has several functions that simplify the automatic gain control (AGC) function in the system receiver. The fast detect feature allows fast overrange detection by outputting four bits of input level information with very short latency.
In addition, the programmable threshold detector allows moni-toring of the incoming signal power using the four fast detect bits of the ADC with very low latency. If the input signal level exceeds the programmable threshold, the fine upper threshold indicator goes high. Because this threshold is set from the four MSBs, the user can quickly turn down the system gain to avoid an overrange condition.
The second AGC-related function is the signal monitor. This block allows the user to monitor the composite magnitude of the incoming signal, which aids in setting the gain to optimize the dynamic range of the overall system.
The ADC output data can be routed directly to the two external 14-bit output ports. These outputs can be set from 1.8 V to 3.3 V CMOS or 1.8 V LVDS.
Flexible power-down options allow significant power savings, when desired.
Programming for setup and control is accomplished using a 3-bit SPI-compatible serial interface.
The AD9640 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.
Product Highlights
- Integrated dual 14-bit, 80/105/125/150 MSPS ADC.
- Fast overrange detect and signal monitor with serial output.
- Signal monitor block with dedicated serial output mode.
- Proprietary differential input that maintains excellent SNR performance for input frequencies up to 450 MHz.
- Operation from a single 1.8 V supply and a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families.
- A standard serial port interface that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, and voltage reference mode.
- Pin compatibility with the AD9627, AD9627-11, and the AD9600 for a simple migration from 14 bits to 12 bits, 11 bits, or 10 bits.
Applications
- Communications
- Diversity radio systems
- Multimode digital receivers
GSM, EDGE, WCDMA, LTE,
CDMA2000, WiMAX, TD-SCDMA - I/Q demodulation systems
- Smart antenna systems
- General-purpose software radios
- Broadband data applications
产品生命周期
量产
该产品系列中至少有一个型号已量产并可供采购。该产品适合用于新设计,但也可能有更新的替代产品。
评估套件 (1)
参考资料
-
AN-905: VisualAnalog™转换器评估工具1.0版用户手册8/18/2020
-
CDMA2000多载波系统可行性研究 (Rev. AN-808)3/22/2018
-
AN-742: Frequency Domain Response of Switched-Capacitor ADCs (Rev. C)2/14/2015
-
AN-835: 高速ADC测试和评估 (Rev. 0)6/9/2013
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AN-1234: 双中频增益模块ADL5534与高速ADC AD9640的接口 (Rev. B)5/8/2013
-
AN-1142: 高速ADC PCB布局布线技巧 (Rev. 0)2/2/2012
-
AN-878: 高速ADC SPI控制软件[中文版] (Rev. A)11/13/2007
-
AN-282: 采样数据系统基本原理[中文版] (Rev. A)11/9/2007
-
AN-737: 如何用ADIsimADC完成ADC建模 (Rev. B)11/9/2007
-
AN-807: 多载波WCDMA的可行性 (Rev. 0)11/9/2007
-
Multicarrier CDMA2000 Feasibility (Rev. AN-808)11/9/2007
-
AN-827: 放大器与开关电容ADC接口的匹配方法[中文版] (Rev. 0)11/9/2007
-
AN-935: ADC变压器耦合前端设计[中文版] (Rev. 0)10/8/2007
-
AN-812: 基于微控制器的串行端口接口(SPI®)启动电路 (Rev. 0)9/20/2006
-
• Software Download (zip, 21,702,560 bytes)
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AN-851: 一种WiMax双下变频IF采样接收机设计方案[中文版] (Rev. 0)7/26/2006
-
AN-715: 走近IBIS模型:什么是IBIS模型?它们是如何生成的? (Rev. 0)12/14/2004
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AN-345: 低频和高频电路接地12/6/2004
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AN-756: 系统采样以及时钟相位噪声和抖动的影响[中文版] (Rev. 0)12/2/2004
-
AN-741: 鲜为人知的相位噪声特性11/29/2004
-
CN-00499/16/2010
工具及仿真模型
Virtual Eval - BETA
Virtual Eval是一款网络应用程序,可帮助设计人员评估ADC和DAC产品。 利用ADI公司服务器上的详细模型,Virtual Eval在几秒内可仿真关键部件的性能特征。 对工作条件(如输入音和外部抖动)以及器件特性(如增益或数字下变频)进行配置。 性能特征包括噪声、失真和分辨率、FFT、时序图、频率响应图等。

IBIS模型
AD9640 IBIS Models
S参数
设计工具
ADIsimRF是一款简单易用的RF信号链计算工具。可以计算和导出多达50级的信号链级联增益、噪声、失真和功耗并绘制其曲线。ADIsimRF还包括丰富的ADI射频和混合信号元件的器件模型数据库。
对于正在选择或评估高速ADC的设计工程师,VisualAnalog™是一个将一组功能强大的仿真和数据分析工具与一个用户友好的图形界面集成在一起的软件包。
配套产品推荐
AD9640 配套产品
设计资源
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Part Number | Material Declaration | Reliability Data | Pin/Package Drawing | CAD Symbols, Footprints & 3D Models |
---|---|---|---|---|
AD80192ABCPZ-155 | 材料声明 | 质量和可靠性 | 64-Lead LFCSP (9mm x 9mm w/ EP) | |
AD9640ABCPZ-105 | 材料声明 | 质量和可靠性 | 64-Lead LFCSP (9mm x 9mm w/ EP) | |
AD9640ABCPZ-125 | 材料声明 | 质量和可靠性 | 64-Lead LFCSP (9mm x 9mm w/ EP) | |
AD9640ABCPZ-150 | 材料声明 | 质量和可靠性 | 64-Lead LFCSP (9mm x 9mm w/ EP) | |
AD9640ABCPZ-80 | 材料声明 | 质量和可靠性 | 64-Lead LFCSP (9mm x 9mm w/ EP) | |
AD9640ABCPZRL7-105 | 材料声明 | 质量和可靠性 | 64-Lead LFCSP (9mm x 9mm w/ EP) | |
AD9640ABCPZRL7-125 | 材料声明 | 质量和可靠性 | 64-Lead LFCSP (9mm x 9mm w/ EP) | |
AD9640ABCPZRL7-80 | 材料声明 | 质量和可靠性 | 64-Lead LFCSP (9mm x 9mm w/ EP) | |
Wafer Fabrication Data |
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