AD9640
量产14-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter
- 产品模型
- 8
产品详情
- 信噪比(SNR):71.8 dBc(72.8 dBFS,至70 MHz、125 MSPS)
- 无杂散动态范围(SFDR):85 dBc (至70 MHz、125 MSPS)
- 低功耗:750 mW (125 MSPS)
- 信噪比(SNR):71.6 dBc(72.6 dBFS,至70 MHz、150 MSPS)
- 无杂散动态范围(SFDR):84 dBc (至70 MHz、150 MSPS)
- 低功耗:820 mW (150 MSPS)
- 1.8 V模拟电源供电
- 1.8 V至3.3V CMOS输出电源或1.8 V LVDS输出电源
- 1至8整数输入时钟除法器
- 中频采样频率达450 MHz
- ADC内部基准电压源
- 集成ADC采样保持输入
- 灵活的模拟输入范围:1 V p-p至2 V p-p
- 欲了解更多特性,请参考数据手册
The AD9640 is a dual 14-bit, 80/105/125/150 MSPS analog-to-digital converter (ADC). The AD9640 is designed to support communications applications where low cost, small size, and versatility are desired.
The dual ADC core features a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth differential sample-and-hold analog input amplifiers supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations. A duty cycle stabilizer is provided to compen-sate for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.
The AD9640 has several functions that simplify the automatic gain control (AGC) function in the system receiver. The fast detect feature allows fast overrange detection by outputting four bits of input level information with very short latency.
In addition, the programmable threshold detector allows moni-toring of the incoming signal power using the four fast detect bits of the ADC with very low latency. If the input signal level exceeds the programmable threshold, the fine upper threshold indicator goes high. Because this threshold is set from the four MSBs, the user can quickly turn down the system gain to avoid an overrange condition.
The second AGC-related function is the signal monitor. This block allows the user to monitor the composite magnitude of the incoming signal, which aids in setting the gain to optimize the dynamic range of the overall system.
The ADC output data can be routed directly to the two external 14-bit output ports. These outputs can be set from 1.8 V to 3.3 V CMOS or 1.8 V LVDS.
Flexible power-down options allow significant power savings, when desired.
Programming for setup and control is accomplished using a 3-bit SPI-compatible serial interface.
The AD9640 is available in a 64-lead LFCSP and is specified over the industrial temperature range of −40°C to +85°C.
Product Highlights
- Integrated dual 14-bit, 80/105/125/150 MSPS ADC.
- Fast overrange detect and signal monitor with serial output.
- Signal monitor block with dedicated serial output mode.
- Proprietary differential input that maintains excellent SNR performance for input frequencies up to 450 MHz.
- Operation from a single 1.8 V supply and a separate digital output driver supply to accommodate 1.8 V to 3.3 V logic families.
- A standard serial port interface that supports various product features and functions, such as data formatting (offset binary, twos complement, or gray coding), enabling the clock DCS, power-down, and voltage reference mode.
- Pin compatibility with the AD9627, AD9627-11, and the AD9600 for a simple migration from 14 bits to 12 bits, 11 bits, or 10 bits.
Applications
- Communications
- Diversity radio systems
- Multimode digital receivers
GSM, EDGE, WCDMA, LTE,
CDMA2000, WiMAX, TD-SCDMA - I/Q demodulation systems
- Smart antenna systems
- General-purpose software radios
- Broadband data applications
参考资料
数据手册 1
应用笔记 18
技术文章 3
产品亮点 1
评估设计文件 1
产品亮点 1
非常见问题 1
模拟对话 1
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产品型号 | 引脚/封装图-中文版 | 文档 | CAD 符号,脚注和 3D模型 |
---|---|---|---|
AD80192ABCPZ-155 | 64-Lead LFCSP (9mm x 9mm w/ EP) | ||
AD9640ABCPZ-105 | 64-Lead LFCSP (9mm x 9mm w/ EP) | ||
AD9640ABCPZ-125 | 64-Lead LFCSP (9mm x 9mm w/ EP) | ||
AD9640ABCPZ-150 | 64-Lead LFCSP (9mm x 9mm w/ EP) | ||
AD9640ABCPZ-80 | 64-Lead LFCSP (9mm x 9mm w/ EP) | ||
AD9640ABCPZRL7-105 | 64-Lead LFCSP (9mm x 9mm w/ EP) | ||
AD9640ABCPZRL7-125 | 64-Lead LFCSP (9mm x 9mm w/ EP) | ||
AD9640ABCPZRL7-80 | 64-Lead LFCSP (9mm x 9mm w/ EP) |
产品型号 | 产品生命周期 | PCN |
---|---|---|
未找到匹配项目 | ||
6月 26, 2023 - 23_0025 Package Outline Drawing and Data Sheet Revision for Select LFCSP Products in Amkor |
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AD80192ABCPZ-155 | 量产 | |
AD9640ABCPZ-105 | 量产 | |
AD9640ABCPZ-125 | 量产 | |
AD9640ABCPZ-150 | 量产 | |
AD9640ABCPZ-80 | 量产 | |
AD9640ABCPZRL7-125 | 量产 | |
AD9640ABCPZRL7-80 | 量产 | |
7月 27, 2020 - 20_0126 Conversion of Select Sizes LFCSP Products from Punched to Sawn and Transfer of Assembly Site to ASE Korea |
||
AD80192ABCPZ-155 | 量产 | |
AD9640ABCPZ-105 | 量产 | |
AD9640ABCPZ-125 | 量产 | |
AD9640ABCPZ-150 | 量产 | |
AD9640ABCPZ-80 | 量产 | |
AD9640ABCPZRL7-125 | 量产 | |
AD9640ABCPZRL7-80 | 量产 | |
1月 29, 2014 - 14_0014 ADI Corporate Obsolescence Notice-January 2014 (Standard Products) |
||
AD9640ABCPZRL7-105 | 过期 |
这是最新版本的数据手册
硬件生态系统
部分模型 | 产品周期 | 描述 |
---|---|---|
单端转差分放大器 2 | ||
ADA4937-1 | 推荐新设计使用 | 超低失真差分ADC驱动器(单通道) |
ADA4938-1 | 推荐新设计使用 | 超低失真差分ADC驱动器(单通道) |
全差分放大器 1 | ||
AD8352 | 推荐新设计使用 | 2 GHz超低失真差分射频/中频放大器 |
时钟产生器件 3 | ||
AD9510 | 推荐新设计使用 | 1.2 GHz时钟分配IC,PLL内核,分频器,延迟调整,8路输出 |
AD9511 | 推荐新设计使用 | 1.2 GHz时钟分配IC,PLL内核,分频器,延迟调整,5路输出 |
AD9512 | 推荐新设计使用 | 1.2 GHz时钟分配IC、2路1.6 GHz输入、分频器、延迟调整、5路输出 |
时钟分配器件 3 | ||
AD9513 | 推荐新设计使用 | 800 MHz时钟分配IC,分频器,延迟调整,三路输出 |
AD9514 | 推荐新设计使用 | 1.6 GHz时钟分配IC、分频器、延迟调整、3路输出 |
AD9515 | 推荐新设计使用 | 1.6 GHz时钟分配IC,分频器,延迟调整,两路输出 |
数字控制VGA 2 | ||
AD8376 | 推荐新设计使用 | 超低失真IF双通道VGA |
AD8372 | 推荐新设计使用 | 41dB增益范围、1 dB步长、可编程双通道VGA |
增益模块 1 | ||
ADL5534 | 推荐新设计使用 | 20 MHz 至500 MHz 中频放大器 |
工具及仿真模型
Virtual Eval - BETA
Virtual Eval是一款网络应用程序,可帮助设计人员评估ADC和DAC产品。 利用ADI公司服务器上的详细模型,Virtual Eval在几秒内可仿真关键部件的性能特征。 对工作条件(如输入音和外部抖动)以及器件特性(如增益或数字下变频)进行配置。 性能特征包括噪声、失真和分辨率、FFT、时序图、频率响应图等。
打开工具AD9640 IBIS Models 3
- AD9640CPZ (All Speed Grades) - 3.3V Outputs
- AD9640CPZ (All Speed Grades) - 1.8V CMOS
- AD9640CPZ (All Speed Grades) - 1.8V LVDS
Visual Analog
对于正在选择或评估高速ADC的设计工程师,VisualAnalog™是一个将一组功能强大的仿真和数据分析工具与一个用户友好的图形界面集成在一起的软件包。
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