AD3552R

推荐新设计使用

双路 16 位 33 MUPS 多跨度多 IO SPI DAC

数据手册 (Rev. B) 产品选型表
产品模型
2
产品技术资料帮助

ADI公司所提供的资料均视为准确、可靠。但本公司不为用户在应用过程中侵犯任何专利权或第三方权利承担任何责任。技术指标的修改不再另行通知。本公司既没有含蓄的允许，也不允许借用ADI公司的专利或专利权的名义。本文出现的商标和注册商标所有权分别属于相应的公司。
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产品详情

  • 16 位分辨率
  • 快速模式下33 MUPS的单路速率
  • 精确模式下 22 MUPS 的单路速率
  • 小信号建立时间 65ns，精确度 0.1%
  • 大信号建立时间 100ns，精确度 0.1%
  • 超小毛刺：< 50 pV×s
  • 超低时延：5 ns
  • 总谐波失真：1 kHz 时为 −105 dB
  • 配置度高的输出电压跨度和失调
  • 1.2V 和 1.8V 逻辑电平兼容
  • 单频段（经典）、双频段和四频段 SPI 模式
  • 多个误差检测器，包括模拟和数字域
  • 2.5 V 内部电压基准，10 ppm/°C 最大温度系数
  • 5 mm × 5 mm LFCSP
AD3552R
双路 16 位 33 MUPS 多跨度多 IO SPI DAC
AD3552R Functional Block Diagram AD3552R Pin Configuration
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参考资料

数据手册 1

用户手册 1

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软件资源

Mbed支持 1

硬件生态系统

部分模型 产品周期 描述
串联基准电压源 1
ADR4525
量产 超低噪声、高精度2.5V基准电压源
低输入偏置电流运算放大器(≤100 pA) 1
AD8065
量产 高性能、145 MHz FastFET™运算放大器
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工具及仿真模型

LTspice 1

LTspice中提供以下器件型号：

  • AD3552R

IBIS 模型 1

LTspice

LTspice®是一款强大高效的免费仿真软件、原理图采集和波形观测器，为改善模拟电路的仿真提供增强功能和模型。

评估套件

eval board
schematic 1
schematic 2
schematic 3
schematic 4
AD-PAARRAY3552R-SL

RF Front-end GaN Power Amplifier Biasing, Protection, and Control Reference Design

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特性和优点

  • Designed to cover full Tx signal chains with integrated MCU and user-friendly GUI for faster and easier integration
  • Supports fault event protection - overvoltage (OV), overcurrent (OC), and overtemperature (OT)
  • Supports ultrafast sub-µs GaN gate voltage switching ~ (<1 µs)
  • Supports ultrafast (<10 µs) fault event protection from detection up to GaN gate pinch-off
  • Wide range of gate bias voltages from -10 V to +10 V
  • Configurable power-up and power-down sequence

产品详情

The AD-PAARRAY3552R-SL reference design provides control, protection, and proper biasing sequence for GaN power amplifier (PA) arrays. The design incorporates the AD3553R high-speed, dual-channel, 16-bit DAC to support the ultrafast sub-µs voltage settling time of GaN gates.

Key fault events, including overvoltage, overcurrent, and overtemperature, are effectively managed by the LTC7000, a static switch driver responsible for system fault protection.

The on-board MAX32666 ultralow-power ARM® Cortex®-M4 microprocessor provides essential debug and programming features for a comprehensive software development experience with the system. The system's firmware is built on ADI's open-source no-OS framework and includes a user-friendly graphical interface (GUI) for evaluation. Updates are easily applied through an SWD UART bootloader, streamlining prototyping.

The system can be powered by an external +48 V supply, requiring high current capabilities.

APPLICATIONS

  • 5G massive MIMOs
  • Macro base stations
Specifications
Fault Events
Fault Default Limit
Overvoltage +55 V
Overcurrent 3.5 A
Overtemperature 75°C
Output Ports
Port Name No. of ports
GaN gate ports 6
+48 V Gan drain ports 4
+5 V ports 5
Enable ports 2
Power Supply
External +48 V DC at 5 A
Operating Conditions
Temperature Range 45°C to +75°C

eval board
schematic 5
schematic 6
schematic 7
EVAL-AD3552R

AD3552R-16的评估板是一款低漂移超快16位精确度的电流输出数模转换器（DAC）。

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特性和优点

  • 适用于AD3552R的功能完备的评估板。
  • 两种跨阻放大器可选
  • 可选跨阻增益
  • 板载或外部电源
  • 板载或外部基准电压
  • 时钟和触发输入实现与外部时钟同步
  • 与控制器板SDP-H1匹配

产品详情

EVAL-AD3552RFMCxZ是一款用于AD3552R超快16位精密DAC的评估板。该评估板有两种变体版本：​实现更高速度的EDITOREVAL-AD3552RFMC1Z和实现更高精度的EVALAD3552RFMC2Z，唯一区别在于跨阻放大器及其对应的反馈电容器。

该评估板实现DAC所有输出范围的测试、波形生成、电源和基准选项。

EVAL-AD3552RFMCxZ通过系统演示平台（SDP- H1板）连接到PC的USB端口。也可通过P5位置的排针接头连接到不同的控制器板。
AD-PAARRAY3552R-SL
RF Front-end GaN Power Amplifier Biasing, Protection, and Control Reference Design
AD-PAARRAY3552R-SL Block Diagram AD-PAARRAY3552R-SL Board Photo Angle View AD-PAARRAY3552R-SL Board Photo Top View AD-PAARRAY3552R-SL Board Photo Bottom View
EVAL-AD3552R
AD3552R-16的评估板是一款低漂移超快16位精确度的电流输出数模转换器（DAC）。
AD3552R Evaluation Board - Angle View AD3552R Evaluation Board - Top View AD3552R Evaluation Board - Bottom View

参考电路

Figure 1. CN0585 Simplified Block Diagram
Figure 1. CN0585 Simplified Block Diagram
EVAL-CN0585-FMCZ Angle View
EVAL-CN0585-FMCZ Bottom View
EVAL-CN0585-FMCZ Top View
CN0585 参考设计

Quad Channel, Low Latency, Data Acquisition and Signal Generation Module

查看参考设计详情

特性和优点

  • 4 Analog Input Channels with Configurable Voltage Ranges
  • 4 Analog Output Channels with Configurable Voltage Ranges
  • 200 ns Latency between ADC Measurement and DAC Settling
  • Analog Front End Interface Connector
  • Modeling and Simulation Compatible with MATLAB and Python
  • FMC Connector Interface to FPGA

使用部分

资料

设计和集成工具

视频

  • lazy blur
    VIDEO · 2022-10-31 03:03
    Low Latency Test and Measurement Kit – Hardware in the Loop
  • lazy blur
    VIDEO · 2023-04-03 03:08
    Personalized Low Latency Hardware in the Loop (HiL) Solution
Figure 1. Simplified Block Diagram
Figure 1. Simplified Block Diagram
CN0584 Kit
CN0584 - Angle View
CN0584 - Top View
CN0584 - Bottom View
CN0584 参考设计

Precision Low Latency Development Kit

查看参考设计详情

特性和优点

  • 4 Analog Input Channels with Configurable Voltage Ranges
  • 4 Analog Output Channels with Configurable Voltage Ranges
  • 250 ns Latency between ADC Measurement and DAC Settling
  • Analog Front End Board Modeling and Simulation Compatible with MATLAB and Python in Rx or Tx Paths
  • All Power and Digital Connections provided by the Interface Connector

使用部分

资料

设计和集成工具

视频

  • lazy blur
    VIDEO · 2023-04-03 03:08
    Personalized Low Latency Hardware in the Loop (HiL) Solution
  • lazy blur
    VIDEO · 2022-10-31 03:03
    Low Latency Test and Measurement Kit – Hardware in the Loop
CN0585
Quad Channel, Low Latency, Data Acquisition and Signal Generation Module
Figure 1. CN0585 Simplified Block Diagram
EVAL-CN0585-FMCZ Angle View
EVAL-CN0585-FMCZ Bottom View
EVAL-CN0585-FMCZ Top View
CN0584
Precision Low Latency Development Kit
Figure 1. Simplified Block Diagram
CN0584 Kit
CN0584 - Angle View
CN0584 - Top View
CN0584 - Bottom View

最新评论

46 周前
实际的settling time较长是datasheet上的10倍
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